A network-on-Chip system-level simulation environment supporting asynchronous router

2007 ◽  
Author(s):  
Ling Xin ◽  
Chiu-Sing Choy
Keyword(s):  
Network On Chip ◽  
System Level ◽  
Simulation Environment ◽  
System Level Simulation ◽  
On Chip

scholarly journals Wireless Network On-Chips History-Based Traffic Prediction for Token Flow Control and Allocation

2019 ◽  
Vol 18 (3) ◽  
pp. 21-26
Author(s):  
Ayodeji Ireti Fasiku ◽  
Muhammad Nadzir Bin Marsono ◽  
Paulson Eberechukwu Numan ◽  
Asrani Lit ◽  
Shahrizal Rusli
Keyword(s):  
Wireless Network ◽  
Network On Chip ◽  
System Level ◽  
Medium Access ◽  
Traffic Demand ◽  
System Level Simulation ◽  
Wireless Medium ◽  
Wireless Interfaces ◽  
On Chip ◽  
Prediction Mechanism

Wireless network-on-chip (WiNoC) uses a wireless backbone on top of the traditional wired-based NoC which demonstrated high scalability. WiNoC introduces long-range single-hop link connecting distanced core and high bandwidth radio frequency interconnects that reduces multi-hop communication in conventional wired-based NoC. However, to ensure full benefits of WiNoC technology, there is a need for fair and efficient Medium Access Control (MAC) mechanism to enhance communication in the wireless Network-on-Chip. To adapt to the varying traffic demands from the applications running on a multicore environment, MAC mechanisms should dynamically adjust the transmission slots of the wireless interfaces (WIs), to ensure efficient utilization of the wireless medium in a WiNoC. This work presents a prediction model that improves MAC mechanism to predict the traffic demand of the WIs and respond accordingly by adjusting transmission slots of the WIs. This research aims to reduce token waiting time and inefficient decision making for radio hub-to-hub communication and congestion-aware routing in WiNoC to enhance end to end latency. Through system level simulation, we will show that the dynamic MAC using an History-based prediction mechanism can significantly improve the performance of a WiNoC in terms of latency and network throughput compared to the state-of-the-art dynamic MAC mechanisms.

A Heterogeneous System-Level Power Macro-Modeling for Network-on-Chip Router

2011 ◽  
Author(s):  
Ning Wu ◽  
Fang Zhou ◽  
Ying Zhang ◽  
Fen Ge
Keyword(s):  
Estimation Error ◽  
Low Power Design ◽  
Network On Chip ◽  
Structure Design ◽  
System Level ◽  
Power Model ◽  
Flow State ◽  
Power Extraction ◽  
Macro Modeling ◽  
On Chip

A heterogeneous macro-model for power extraction of the Network-on-Chip router at system level is proposed, with higher accuracy to overcome the shortcoming of existing architecture-level power simulators, which is aimed to evaluate the network performance rapidly and guide the communication structure design. Each module of the router is modeled by different methods according to different characteristics. The input/output ports, the routing algorithm and the crossbar switch are established by multiple linear regression because of their single data flow state. The arbiter is established based on BP neural network due to its numerous states. Several experiments with different traffic loads and input sequences are carried out to verify the power model. Experimental results show that our power model is higher speed over the gate-level simulation, and the average estimation error is 5.0%. As a case study, we use the proposed model to evaluate the performance of different core mappings for H.264 decoder in system-level low power design.

scholarly journals Ferrimagnetic Synapse Devices for Fast and Energy-Efficient On-Chip Learning on An Analog-Hardware Neural Network

2021 ◽  
Author(s):  
Upasana Sahu ◽  
Naven Sisodia ◽  
Janak Sharda ◽  
Pranaba Kishor Muduli ◽  
Debanjan Bhowmik
Keyword(s):  
Domain Wall ◽  
Energy Efficient ◽  
Velocity Ratio ◽  
Domain Wall Motion ◽  
System Level ◽  
System Level Simulation ◽  
On Chip ◽  
Experimental Findings ◽  
Fully Connected ◽  
Hardware Neural Network

we have modeled domain-wall motion in ferrimagnetic and ferromagnetic devices through micro magnetics and shown that the domain-wall velocity can be 2–2.5X faster in the ferrimagnetic device compared to the ferromagnetic device. We also show that this velocity ratio is consistent with recent experimental findings Because of such a velocity ratio, when such devices are used as synapses in the crossbar-array-based fully connected network, our system-level simulation here shows that a ferrimagnet-synapse-based crossbar offers 4X faster (for the same energy efficiency) or 4X more energy-efficient (for the same speed) learning when compared to the ferromagnet-synapse-based crossbar.

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