Energy-Efficient Digital Filtering Using ML-based Error Correction (ML-EC) Technique

Author(s):  
Jun Won Choi ◽  
Byonghyo Shim ◽  
Andrew C. Singer ◽  
Nam Ik Cho
2021 ◽  
Vol 2 (2) ◽  

Techniques for reducing power consumption in digital circuits that underly automatic control of modern engineering systems are of paramount importance due to the simultaneously growing demands for portable multimedia devices and energy conservation. Digital filters, being ubiquitous in such devices, are thus a prime candidate for low power design. We review an algorithmic approach to low power frequency-selective digital filtering, an essential ingredient for energy efficient technological innovation in many domains.


2021 ◽  
Vol 2 (2) ◽  

Techniques for reducing power consumption in digital circuits that underly automatic control of modern engineering systems are of paramount importance due to the simultaneously growing demands for portable multimedia devices and energy conservation. Digital filters, being ubiquitous in such devices, are thus a prime candidate for low power design. We review an algorithmic approach to low power frequency-selective digital filtering, an essential ingredient for energy efficient technological innovation in many domains.


Author(s):  
Antonio Malacarne ◽  
Vito Sorianello ◽  
Aidan Daly ◽  
Benjamin Kögel ◽  
Markus Ortsiefer ◽  
...  

2016 ◽  
Vol 16 (4) ◽  
pp. 183-189 ◽  
Author(s):  
Magdalena Dobrzańska ◽  
Paweł Dobrzański ◽  
Mirosław Śmieszek ◽  
Paweł Pawlus

AbstractIn this article the issues related to mapping the route and error correction in automated guided vehicle (AGV) movement have been discussed. The nature and size of disruption have been determined using the registered runs in experimental studies. On the basis of the analysis a number of numerical runs have been generated, which mapped possible to obtain runs in a real movement of the vehicle. The obtained data set has been used for further research. The aim of this paper was to test the selected methods of digital filtering on the same data set and determine their effectiveness. The results of simulation studies have been presented in the article. The effectiveness of various methods has been determined and on this basis the conclusions have been drawn.


Author(s):  
J. H. Kong ◽  
J. J. Ong ◽  
L.-M. Ang ◽  
K. P. Seng

This chapter presents low complexity processor designs for energy-efficient security and error correction for implementation on wireless sensor networks (WSN). WSN nodes have limited resources in terms of hardware, memory, and battery life span. Small area hardware designs for encryption and error-correction modules are the most preferred approach to meet the stringent design area requirement. This chapter describes Minimal Instruction Set Computer (MISC) processor designs with a compact architecture and simple hardware components. The MISC is able to make use of a small area of the FPGA and provides a processor platform for security and error correction operations. In this chapter, two example applications, which are the Advance Encryption Standard (AES) and Reed Solomon (RS) algorithms, were implemented onto MISC. The MISC hardware architecture for AES and RS were designed and verified using the Handel-C hardware description language and implemented on a Xilinx Spartan-3 FPGA.


Sign in / Sign up

Export Citation Format

Share Document