Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures

Network-on-Chip (NoC) has been proposed as a viable solution to the communication challenges on System-on-Chips (SoCs). As the communication paradigm of SoC, NoCs performance depends mainly on the type of routing algorithm chosen. In this paper different categories of routing algorithms were compared. These include XY routing, OE turn model adaptive routing, DyAD routing and Age-Aware adaptive routing. By varying the load at different Packet Injection Rate (PIR) under random traffic pattern, comparison was conducted using a 4 × 4 mesh topology. The Noxim simulator, a cycle accurate systemC based simulator was employed. The packets were modeled as a Poisson distribution; first-in-first-out (FIFO) input buffer channel with a depth of five (5) flits and a flit size of 32 bits; and a packet size of 3 flits respectively. The simulation time was 10,000 cycles. The findings showed that the XY routing algorithm performed better when the PIR is low. In a similar vein, the DyAD routing and Age-aware algorithms performed better when the load i.e. PIR is high.

Download Full-text

An Overview of Multicast Routing Algorithms in Network on Chip

Learning and Analytics in Intelligent Systems - Intelligent Computing Paradigm and Cutting-edge Technologies ◽

10.1007/978-3-030-65407-8_14 ◽

2021 ◽

pp. 163-178

Author(s):

Sumitra Velayudham ◽

Sivakumar Rajagopal ◽

Swaminathan Kathirvel ◽

Basim Alhadidi

Keyword(s):

Multicast Routing ◽

Network On Chip ◽

Routing Algorithms ◽

On Chip

Download Full-text

AOCR: adaptive on chip router algorithm for multicore domain controller platform

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i4.13477 ◽

2018 ◽

Vol 7 (4) ◽

pp. 2246

Author(s):

T Shanmuganathan ◽

U Ramachandraiah

Keyword(s):

Energy Efficient ◽

Cost Reduction ◽

Network Performance ◽

Rapid Development ◽

Routing Algorithm ◽

Routing Algorithms ◽

Core Domain ◽

Latency Reduction ◽

Increasing Demand ◽

On Chip

In the recent years, with the rapid development of semiconductor technologies and increasing demand for more effective multi-Core Domain Controller platforms, there is a clear demand for effective routing algorithms that can be used to route the packets between these platforms, while enhancing an on chip network performance, achieving a better latency and throughput. This paper proposes an adaptive on Chip Router algorithm with a simple adaptive routing algorithm based on runtime weighted arbitration and resource allocation methodology, where the routing decisions are minimized for applications-specific MDCU platforms. The proposed scheme is evaluated by simulations and its performance in terms of latency, area, power consumption and cost reduction per vehicle are presented. The results show that, 24.5% of latency reduction, 62.25% area utilization optimization and 63.76% of energy efficient compare with existing methods.

Download Full-text