scholarly journals AOCR: adaptive on chip router algorithm for multicore domain controller platform

2018 ◽  
Vol 7 (4) ◽  
pp. 2246
Author(s):  
T Shanmuganathan ◽  
U Ramachandraiah
Keyword(s):  
Energy Efficient ◽  
Cost Reduction ◽  
Network Performance ◽  
Rapid Development ◽  
Routing Algorithm ◽  
Routing Algorithms ◽  
Core Domain ◽  
Latency Reduction ◽  
Increasing Demand ◽  
On Chip

In the recent years, with the rapid development of semiconductor technologies and increasing demand for more effective multi-Core Domain Controller platforms, there is a clear demand for effective routing algorithms that can be used to route the packets between these platforms, while enhancing an on chip network performance, achieving a better latency and throughput. This paper proposes an adaptive on Chip Router algorithm with a simple adaptive routing algorithm based on runtime weighted arbitration and resource allocation methodology, where the routing decisions are minimized for applications-specific MDCU platforms. The proposed scheme is evaluated by simulations and its performance in terms of latency, area, power consumption and cost reduction per vehicle are presented. The results show that, 24.5% of latency reduction, 62.25% area utilization optimization and 63.76% of energy efficient compare with existing methods.  

Comparative Performance Analysis of 
Selected Routing Algorithms by Load Variation of 2-Dimensional Mesh Topology Based 
Network-On-Chip

2021 ◽  
Vol 20 (3) ◽  
pp. 1-6
Author(s):  
Mohammed Shaba Saliu ◽  
Muyideen Omuya Momoh ◽  
Pascal Uchenna Chinedu ◽  
Wilson Nwankwo ◽  
Aliu Daniel
Keyword(s):  
Routing Algorithm ◽  
Adaptive Routing ◽  
Injection Rate ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Comparative Performance ◽  
Traffic Pattern ◽  
Mesh Topology ◽  
Similar Vein ◽  
On Chip

Network-on-Chip (NoC) has been proposed as a viable solution to the communication challenges on System-on-Chips (SoCs). As the communication paradigm of SoC, NoCs performance depends mainly on the type of routing algorithm chosen. In this paper different categories of routing algorithms were compared. These include XY routing, OE turn model adaptive routing, DyAD routing and Age-Aware adaptive routing.  By varying the load at different Packet Injection Rate (PIR) under random traffic pattern, comparison was conducted using a 4 × 4 mesh topology. The Noxim simulator, a cycle accurate systemC based simulator was employed. The packets were modeled as a Poisson distribution; first-in-first-out (FIFO) input buffer channel with a depth of five (5) flits and a flit size of 32 bits; and a packet size of 3 flits respectively. The simulation time was 10,000 cycles. The findings showed that the XY routing algorithm performed better when the PIR is low.  In a similar vein, the DyAD routing and Age-aware algorithms performed better when the load i.e. PIR is high.

scholarly journals DCAR: DTN Congestion Avoidance Routing Algorithm Based on Tokens in an Urban Environment

2017 ◽  
Vol 2017 ◽  
pp. 1-9
Author(s):  
Hezhe Wang ◽  
Hongwu Lv ◽  
Huiqiang Wang ◽  
Guangsheng Feng
Keyword(s):  
Network Performance ◽  
Routing Algorithm ◽  
Relay Node ◽  
Routing Algorithms ◽  
Buffer Size ◽  
Destination Node ◽  
Delivery Ratio ◽  
Movement Trajectory ◽  
Average Delay ◽  
Urban Scenario

When a delay/disruption tolerant network (DTN) is applied in an urban scenario, the network is mainly composed of mobile devices carried by pedestrians, cars, and other vehicles, and the node’s movement trajectory is closely related to its social relationships and regular life; thus, most existing DTN routing algorithms cannot show efficient network performance in urban scenarios. In this paper, we propose a routing algorithm, called DCRA, which divides the urban map into grids; fixed sink stations are established in specific grids such that the communication range of each fixed sink station can cover a specific number of grids; these grids are defined as a cluster and allocated a number of tokens in each cluster; the tokens in the cluster are controlled by the fixed sink station. A node will transmit messages to a relay node that has a larger remaining buffer size and encounters fixed sink stations or the destination node more frequently after it obtains a message transmit token. Simulation experiments are carried out to verify the performance of the DCAR under an urban scenario, and results show that the DCAR algorithm is superior to existing routing algorithms in terms of delivery ratio, average delay, and network overhead.

Double Stairs: A Fault-Tolerant Routing Algorithm for Networks-on-Chip

2016 ◽  
Vol 25 (06) ◽  
pp. 1650065 ◽  
Author(s):  
Saleh Fakhrali ◽  
Hamid R. Zarandi
Keyword(s):  
Fault Tolerance ◽  
Fault Tolerant ◽  
Routing Algorithm ◽  
Deep Submicron ◽  
Routing Algorithms ◽  
Experimental Results ◽  
Trade Off ◽  
Networks On Chip ◽  
On Chip ◽  
Probabilistic Flooding

Reliability is one of the main concerns in the design of networks-on-chip (NoCs) due to the use of deep submicron technologies in fabrication of such products. This paper presents a new fault-tolerant routing algorithm called double stairs for NoCs. Double stairs routing algorithm is a low overhead routing that has the ability to deal with fault. The proposed routing algorithm makes a redundant copy of each packet at the source node and routes the original and redundant packets in a new partially adaptive routing algorithm. The method is evaluated for various packet injection rates and fault rates. Experimental results show that the proposed routing algorithm offers the best trade-off between performance and fault tolerance compared to other routing algorithms, namely flooding, XYX and probabilistic flooding.

scholarly journals ParRouting: An Efficient Area Partition-Based Congestion-Aware Routing Algorithm for NoCs

Micromachines ◽  
2020 ◽  
Vol 11 (12) ◽  
pp. 1034
Author(s):  
Juan Fang ◽  
Di Zhang ◽  
Xiaqing Li
Keyword(s):  
Routing Algorithm ◽  
Central Area ◽  
Routing Algorithms ◽  
Output Node ◽  
Networks On Chip ◽  
Traffic Pattern ◽  
Key Factor ◽  
Congestion Awareness ◽  
On Chip ◽  
Congestion Aware

Routing algorithms is a key factor that determines the performance of NoC (Networks-on-Chip) systems. Regional congestion awareness routing algorithms have shown great potential in improving the performance of NoC. However, it incurs a significant queuing latency when practitioners use existing regional congestion awareness routing algorithms to make routing decisions, thus degrading the performance of NoC. In this paper, we propose an efficient area partition-based congestion-aware routing algorithm, ParRouting, which aims at increasing the throughput and reducing the latency for NoC systems. First, ParRouting partitions the network into two areas (i.e., edge area and central area.) based on node priorities. Then, for the edge area, ParRouting selects the output node based on different priorities for higher throughput; for the central area, ParRouting selects the node in the low congestion direction as the output node for lower queuing latency. Our experimental results indicate that ParRouting achieves a 53.4% reduction in packet average latency over SPLASH -2 ocean application and improves the saturated throughput by up to 38.81% over a synthetic traffic pattern for an NoC system, compared to existing routing algorithms.

Application of WeChat Mini-Program and Wi-Fi SoC in Agricultural IoT: A Low-Cost Greenhouse Monitoring System

2020 ◽  
Vol 63 (2) ◽  
pp. 325-337
Author(s):  
Lei Zhou ◽  
Zhengjun Qiu ◽  
Yong He
Keyword(s):  
Internet Of Things ◽  
Monitoring System ◽  
High Performance ◽  
Low Cost ◽  
Rapid Development ◽  
Sensor Nodes ◽  
Sensor Data ◽  
Smart Devices ◽  
Increasing Demand ◽  
On Chip

HighlightsA quick solution for developing and deploying custom agricultural IoT systems is proposed.Low-cost and high-performance devices are used for the design of sensor nodes.A mobile application based on WeChat Mini-Program is developed for device and data management.The proposed system brings convenience to both users and developers.Abstract. Increasing demand for automatic management of agricultural production and real-time remote monitoring has increased the need for smart devices, wireless technologies, and sensors. The internet of things (IoT) has emerged as a common technology for the management of multiple devices by multiple users. Some professional solutions are relatively difficult to implement for researchers who are interested in agricultural IoT but do not have requisite skills in computers and electronics. The unfriendliness of the user software limits the practical application of agricultural IoT in China. This article presents a simple solution based on an SoC (system-on-chip) and WeChat mini-program that focuses on low-cost hardware, rapid development, user-friendly application design, and helping developers get a quick start in building a DIY monitoring system. The ESP8266, a high-performance SoC, is used as the microcontroller and Wi-Fi module to transfer the sensor data to a remote server. A WeChat mini-program provides the graphical user interface, enabling users to manage devices and access data by clicking. Users can log into the system using their WeChat accounts and bind devices by scanning QR codes on the devices. Thus, the complex management and device binding in conventional systems can be overcome. The system is easy to be expand and has great potential for greenhouse environmental monitoring in China. Keywords: Greenhouse ambient monitoring, Internet of things, WeChat mini-program, Wi-Fi SoC.

scholarly journals Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

2015 ◽  
Vol 2015 ◽  
pp. 1-16 ◽  
Author(s):  
Feng Wang ◽  
Xiantuo Tang ◽  
Zuocheng Xing
Keyword(s):  
Power Efficiency ◽  
Network Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Leakage Power ◽  
Power Gating ◽  
Load Range ◽  
Communication Architectures ◽  
On Chip ◽  
Many Core

Network-on-Chip (NoC) is one of critical communication architectures for future many-core systems. As technology is continually scaling down, on-chip network meets the increasing leakage power crisis. As a leakage power mitigation technique, power-gating can be utilized in on-chip network to solve the crisis. However, the network performance is severely affected by the disconnection in the conventional power-gated NoC. In this paper, we propose a novel partial power-gating approach to improve the performance in the power-gated NoC. The approach mainly involves a direction-slicing scheme, an improved routing algorithm, and a deadlock recovery mechanism. In the synthetic traffic simulation, the proposed design shows favorable power-efficiency at low-load range and achieves better performance than the conventional power-gated one. For the application trace simulation, the design in the mesh/torus network consumes 15.2%/18.9% more power on average, whereas it can averagely obtain 45.0%/28.7% performance improvement compared with the conventional power-gated design. On balance, the proposed design with partial power-gating has a better tradeoff between performance and power-efficiency.

scholarly journals A Novel Approach for the Design of Fault-Tolerant Routing Algorithms in NoCs: Passage of Faulty Nodes, Not Always Detour

2020 ◽  
Author(s):  
Masaru Fukushi ◽  
Yota Kurokawa
Keyword(s):  
Fault Tolerant ◽  
Routing Algorithm ◽  
Slight Modification ◽  
Routing Algorithms ◽  
Future Research ◽  
Communication Performance ◽  
Novel Approach ◽  
Average Latency ◽  
The Common ◽  
On Chip

Due to the faults in system fabrication and run time, designing an efficient fault-tolerant routing algorithm with the property of deadlock-freeness is crucial for realizing dependable Network-on-Chip (NoC) systems with high communication performance. In this chapter, we introduce a novel approach for the design of fault-tolerant routing algorithms in NoCs. The common idea of the fault-tolerant routing has been undoubtedly to detour faulty nodes, while our approach allows passing through faulty nodes with the slight modification of NoC architecture. As a design example, we present an XY-based routing algorithm with the passage function. To investigate the effect of the approach, we compare the communication performance (i.e. average latency) of the XY-based algorithm with well-known region-based algorithms under the condition of with and without virtual channels. Finally, we provide possible directions of future research on the fault-tolerant routing with the passage function.

scholarly journals Congestion-Aware Routing Algorithm for NoC Using Data Packets

2021 ◽  
Vol 2021 ◽  
pp. 1-11
Author(s):  
Khurshid Ahmad ◽  
Muhammad Athar Javed Sethi ◽  
Rehmat Ullah ◽  
Imran Ahmed ◽  
Amjad Ullah ◽  
...  
Keyword(s):  
Routing Algorithm ◽  
Network On Chip ◽  
Routing Algorithms ◽  
System On Chip ◽  
Multiprocessor System ◽  
Data Packets ◽  
Communication Framework ◽  
Using Data ◽  
On Chip ◽  
Congestion Aware

Network on Chip (NoC) is a communication framework for the Multiprocessor System on Chip (MPSoC). It is a router-based communication system. In NoC architecture, nodes of MPSoC are communicating through the network. Different routing algorithms have been developed by researchers, e.g., XY, intermittent XY, DyAD, and DyXY. The main problems in these algorithms are congestion and faults. Congestion and faults cause delay, which degrades the performance of NoC. A congestion-aware algorithm is used for the distribution of traffic over NoC and for the avoidance of congestion. In this paper, a congestion-aware routing algorithm is proposed. The algorithm works by sending congestion information in the data packet. The algorithm is implemented on a 4 × 4 mesh NoC using FPGA. The proposed algorithm decreases latency, increases throughput, and uses less bandwidth in sharing congestion information between routers in comparison to the existing congestion-aware routing algorithms.

scholarly journals A New Efficient and Reliable Dynamically ReconfigurableNetwork-on-Chip

2012 ◽  
Vol 2012 ◽  
pp. 1-16 ◽  
Author(s):  
Cédric Killian ◽  
Camel Tanougast ◽  
Fabrice Monteiro ◽  
Abbas Dandache
Keyword(s):  
Error Detection ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Data Packet ◽  
Reliable Operation ◽  
Detection Mechanism ◽  
Dynamically Reconfigurable ◽  
On Chip ◽  
Online Error Detection

We present a new reliableNetwork-on-Chip(NoC) suitable forDynamically Reconfigurable Multiprocessors on Chipsystems. The proposedNoCis based on routers performing online error detection of routing algorithm and data packet errors. Our work focuses on adaptive routing algorithms which allow to bypass faulty components or processor elements dynamically implemented inside the network. The proposed routing error detection mechanism allows to distinguish routing errors from bypasses of faulty components. The new router architecture is based on additional diagonal state indications and specific logic blocks allowing the reliable operation of theNoC. The main originality in the proposedNoCis that only the permanently faulty parts of the routers are disconnected. Therefore, our approach maintains a high run time throughput in theNoCwithout data packet loss thanks to a self-loopbackmechanism inside each router.

scholarly journals Energy-Efficient Probabilistic Routing Algorithm for Internet of Things

2014 ◽  
Vol 2014 ◽  
pp. 1-7 ◽  
Author(s):  
Sang-Hyun Park ◽  
Seungryong Cho ◽  
Jung-Ryun Lee
Keyword(s):  
Internet Of Things ◽  
Network Lifetime ◽  
Energy Efficient ◽  
Network Performance ◽  
Routing Algorithm ◽  
Distributed Networks ◽  
Residual Energy ◽  
Aodv Protocol ◽  
Probabilistic Routing ◽  
Key Factor

In the future network with Internet of Things (IoT), each of the things communicates with the others and acquires information by itself. In distributed networks for IoT, the energy efficiency of the nodes is a key factor in the network performance. In this paper, we propose energy-efficient probabilistic routing (EEPR) algorithm, which controls the transmission of the routing request packets stochastically in order to increase the network lifetime and decrease the packet loss under the flooding algorithm. The proposed EEPR algorithm adopts energy-efficient probabilistic control by simultaneously using the residual energy of each node and ETX metric in the context of the typical AODV protocol. In the simulations, we verify that the proposed algorithm has longer network lifetime and consumes the residual energy of each node more evenly when compared with the typical AODV protocol.

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