Robust path delay-fault testability on dynamic CMOS circuits

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.1991.139882 ◽

2002 ◽

Author(s):

P.C. McGeer

Keyword(s):

Cmos Circuits ◽

Delay Fault ◽

Path Delay Fault

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A new classification of path-delay fault testability in terms of stuck-at faults

Journal of Computer Science and Technology ◽

10.1007/bf02973460 ◽

2004 ◽

Vol 19 (6) ◽

pp. 955-964 ◽

Author(s):

Subhashis Majumder ◽

Bhargab B. Bhattacharya ◽

Vishwani D. Agrawal ◽

Michael L. Bushnell

Keyword(s):

New Classification ◽

Delay Fault ◽

Path Delay Fault

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Path Delay Fault Classification

Frontiers in Electronic Testing - Delay Fault Testing for VLSI Circuits ◽

10.1007/978-1-4615-5597-1_5 ◽

1998 ◽

pp. 45-76

Author(s):

Angela Krstić ◽

Kwang-Ting Cheng

Keyword(s):

Fault Classification ◽

Delay Fault ◽

Path Delay Fault

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Path delay fault simulation algorithms for sequential circuits

Proceedings First Asian Test Symposium (ATS `92) ◽

10.1109/ats.1992.224444 ◽

2003 ◽

Author(s):

T.J. Chakraborty ◽

V.D. Agrawal ◽

M.L. Bushnell

Keyword(s):

Fault Simulation ◽

Sequential Circuits ◽

Delay Fault ◽

Path Delay Fault ◽

Simulation Algorithms

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On the design of path delay fault testable combinational circuits

[1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium ◽

10.1109/ftcs.1990.89391 ◽

2002 ◽

Author(s):

A.K. Pramanick ◽

S.M. Reddy

Keyword(s):

Combinational Circuits ◽

Delay Fault ◽

Path Delay Fault

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New advances in path delay fault testing of combinational circuits

Proceedings of IEEE VLSI Test Symposium ◽

10.1109/vtest.1994.292301 ◽

2002 ◽

Author(s):

X. Xie ◽

A. Albicki

Keyword(s):

Combinational Circuits ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Path Delay Fault Testing

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Path Delay Fault Model

High Quality Test Pattern Generation and Boolean Satisfiability ◽

10.1007/978-1-4419-9976-4_8 ◽

2012 ◽

pp. 155-180

Author(s):

Stephan Eggersglüß ◽

Rolf Drechsler

Keyword(s):

Fault Model ◽

Delay Fault ◽

Path Delay Fault

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Parallel concurrent path-delay fault simulation using single-input change patterns

Proceedings of 9th International Conference on VLSI Design ◽

10.1109/icvd.1996.489647 ◽

2002 ◽

Author(s):

M.A. Gharaybeh ◽

M.L. Bushnell ◽

V.D. Agrawal

Keyword(s):

Fault Simulation ◽

Delay Fault ◽

Path Delay Fault ◽

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Path delay fault testing using test points

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/606603.606604 ◽

2003 ◽

Vol 8 (1) ◽

pp. 1-10 ◽

Author(s):

S. Tragoudas ◽

N. Denny

Keyword(s):

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Test Points ◽

Path Delay Fault Testing

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Nonenumerative path delay fault coverage estimation with optimal algorithms

Proceedings International Conference on Computer Design VLSI in Computers and Processors ICCD-97 ◽

10.1109/iccd.1997.628896 ◽

2002 ◽

Author(s):

D. Kagaris ◽

S. Tragoudas ◽

D. Karayiannis

Keyword(s):

Fault Coverage ◽

Optimal Algorithms ◽

Delay Fault ◽

Path Delay Fault ◽

Coverage Estimation ◽

Fault Coverage Estimation

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Non-enumerative path delay fault diagnosis [logic testing]

2003 Design, Automation and Test in Europe Conference and Exhibition ◽

10.1109/date.2003.1253627 ◽

2003 ◽

Author(s):

S. Padmanaban ◽

S. Tragoudas

Keyword(s):

Fault Diagnosis ◽

Delay Fault ◽

Logic Testing ◽

Path Delay Fault

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