Concurrent test scheduling in built-in self-test environment

2003 ◽  
Author(s):  
C.-I.H. Chen ◽  
J.T. Yuen
Keyword(s):  
Test Scheduling ◽  
Test Environment ◽  
Self Test ◽  
Built In Self Test

scholarly journals Test scheduling and control for VLSI built-in self-test

1988 ◽  
Vol 37 (9) ◽  
pp. 1099-1109 ◽  
Author(s):  
G.L. Craig ◽  
C.R. Kine ◽  
K.K. Saluja
Keyword(s):  
Test Scheduling ◽  
Self Test ◽  
Built In Self Test ◽  
And Control

Implementing built-in self-test environment for cores-based digital circuits with Verilog HDL

2012 ◽  
Vol 9 (6) ◽  
pp. 519-528
Author(s):  
Sunil Das ◽  
Liwu Jin ◽  
Mansour Assaf ◽  
Satyendra Biswas ◽  
Emil Petriu
Keyword(s):  
Digital Circuits ◽  
Verilog Hdl ◽  
Test Environment ◽  
Self Test ◽  
Built In Self Test

scholarly journals Design of a Realistic Test Simulator For a Built-In Self Test Environment

2010 ◽  
Vol 7 (2) ◽  
pp. 69 ◽  
Author(s):  
A. Ahmad ◽  
D. Al-Abri
Keyword(s):  
Fault Tolerant ◽  
Low Cost ◽  
Bench Mark ◽  
Test Environment ◽  
Digital Electronics ◽  
Special Software ◽  
Programming Skill ◽  
Self Test ◽  
Built In Self Test ◽  
Fault Grading

 This paper presents a realistic test approach suitable to Design For Testability (DFT) and Built- In Self Test (BIST) environments. The approach is culminated in the form of a test simulator which is capable of providing a required goal of test for the System Under Test (SUT). The simulator uses the approach of fault diagnostics with fault grading procedure to provide the tests. The tool is developed on a common PC platform and hence no special software is required. Thereby, it is a low cost tool and hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any SUT. The developed tool incorporates a flexible Graphical User Interface (GUI) procedure and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational purposes for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safe - reliable - testable digital logic designs. 

Built-In Self-Test and Test Scheduling for Interposer-Based 2.5D IC

2015 ◽  
Vol 20 (4) ◽  
pp. 1-24 ◽  
Author(s):  
Ran Wang ◽  
Krishnendu Chakrabarty ◽  
Sudipta Bhawmik
Keyword(s):  
Test Scheduling ◽  
Self Test ◽  
Built In Self Test

RF Phase Error Built-In-Self-Test for A GSM SOC

2008 ◽  
Vol 1 (4) ◽  
pp. 39-44
Author(s):  
Dallas Webster ◽  
Loi Phan ◽  
Oren Eliezer ◽  
Rick Hudgens ◽  
Donald Lie
Keyword(s):  
Phase Error ◽  
Self Test ◽  
Built In Self Test
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