Test the S27 Benchmark Circuit by Using Built In Self Test and Test Pattern Generation

2014 ◽  
Vol 03 (08) ◽  
pp. 11487-11495
Author(s):  
S. Nagaraju ◽  
Ch.N.L. Sujatha ◽  
J.S.S. Ramaraju
Keyword(s):  
Test Pattern ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Benchmark Circuit ◽  
Self Test ◽  
Built In Self Test

A low power test pattern generation for built-in self-test based circuits

2011 ◽  
Vol 98 (3) ◽  
pp. 301-309 ◽  
Author(s):  
Bo Ye ◽  
Tianwang Li ◽  
Qian Zhao ◽  
Duo Zhou ◽  
Xiaohua Wang ◽  
...  
Keyword(s):  
Low Power ◽  
Test Pattern ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Power Test ◽  
Low Power Test ◽  
Self Test ◽  
Built In Self Test

scholarly journals Low Cost Test Pattern Generation in Scan-Based BIST Schemes

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 314 ◽  
Author(s):  
Guohe Zhang ◽  
Ye Yuan ◽  
Feng Liang ◽  
Sufen Wei ◽  
Cheng-Fu Yang
Keyword(s):  
Test Pattern ◽  
Low Cost ◽  
Pattern Generator ◽  
Pattern Generation ◽  
Low Power Consumption ◽  
Test Pattern Generation ◽  
Hardware Overhead ◽  
Single Input ◽  
Simulation Results ◽  
Self Test

This paper proposes a low-cost test pattern generator for scan-based built-in self-test (BIST) schemes. Our method generates broadcast-based multiple single input change (BMSIC) vectors to fill more scan chains. The proposed algorithm, BMSIC-TPG, is based on our previous work multiple single-input change (MSIC)-TPG. The broadcast circuit expends MSIC vectors, so that the hardware overhead of the test pattern generation circuit is reduced. Simulation results with ISCAS’89 benchmarks and a comparison with the MSIC-TPG circuit show that the proposed BMSIC-TPG reduces the circuit hardware overhead about 50% with ensuring of low power consumption and high fault coverage.

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