DPCLS: Improving Partial Cache Line Sparing with Dynamics for Memory Error Prevention

Author(s):  
Xiaoming Du ◽  
Cong Li
2021 ◽  
Author(s):  
Xiaoming Du ◽  
Cong Li ◽  
Shen Zhou ◽  
Xian Liu ◽  
Xiaohan Xu ◽  
...  

2013 ◽  
Author(s):  
Daniella Karidi ◽  
Steven G. Zecker ◽  
Peter G. Rendell

2017 ◽  
Vol 8 (2) ◽  
pp. 563 ◽  
Author(s):  
Usman Ependi

Heuristic evaluation merupakan salah satu bentuk usability testing perangkat lunak yang dinilai oleh pengguna (evaluator). Dalam melakukan heuristic evaluation instrumen penilaian terdiri dari sepuluh (10) pernyataan dengan lima pilihan jawaban dalam skala severity ratings. Dalam penelitian ini heuristic evaluation terhadap aplikasi Depo Auto 2000 Tanjung Api-Api Palembang yang dilakukan oleh 4 evaluator.  Hasil dari heuristic evaluation dikelompokkan kedalam  masing-masing instrumen yaitu visibility of system status dengan nilai 0,75, match between system and the real world dengan nilai 0,25, user control and freedom dengan nilai 0,25, consistency and standards dengan nilai 0,75, error prevention dengan nilai 1, recognition rather than recall dengan nilai 1,25, flexibility and efficiency of use dengan nilai 0,25, Aesthetic and minimalist design dengan nilai 0,25, help users recognize, diagnose, and recover from errors dengan nilai 1 dan Help and documentation dengan nilai 0. Dari hasil heuristic evaluation yang dilakukan menunjukkan bahwa evaluator memberikan nilai 0 dan 1 aplikasi Depo Atuo 2000 Tanjung Api-Api Palembang. Hasil penilaian tersebut menunjukkan bahwa aplikasi yang buat tidak ada masalah usability dan hanya memiliki cosmetic problem sehingga aplikasi Depo Auto 2000 Tanjung Api Api Palembang  dapat dinyatakan layak untuk didistribusikan kepada pengguna akhir (end user). 


2018 ◽  
pp. 47-53
Author(s):  
B. Z. Shmeylin ◽  
E. A. Alekseeva

In this paper the tasks of managing the directory in coherence maintenance systems in multiprocessor systems with a large number of processors are solved. In microprocessor systems with a large number of processors (MSLP) the problem of maintaining the coherence of processor caches is significantly complicated. This is due to increased traffic on the memory buses and increased complexity of interprocessor communications. This problem is solved in various ways. In this paper, we propose the use of Bloom filters used to accelerate the determination of an element’s belonging to a certain array. In this article, such filters are used to establish the fact that the processor belongs to some subset of the processors and determine if the processor has a cache line in the set. In the paper, the processes of writing and reading information in the data shared between processors are discussed in detail, as well as the process of data replacement from private caches. The article also shows how the addresses of cache lines and processor numbers are removed from the Bloom filters. The system proposed in this paper allows significantly speeding up the implementation of operations to maintain cache coherence in the MSLP as compared to conventional systems. In terms of performance and additional hardware and software costs, the proposed system is not inferior to the most efficient of similar systems, but on some applications and significantly exceeds them.


2018 ◽  
Vol 53 (4) ◽  
pp. 181-195 ◽  
Author(s):  
Gregory J. Duck ◽  
Roland H. C. Yap
Keyword(s):  

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