Intermediate Module Design for Test Module of RND Center Dashboard in EV with FPGA

Abstract Rapidly changing technology highlights the necessity of developing new failure analysis methodologies. This paper will discuss the combination of two techniques, Design for Test (DFT) and Focused Ion Beam (FIB) analysis, as a means for successfully isolating and identifying a series of high impedance failure sites in a 0.35 μm CMOS design. Although DFT was designed for production testing, the failure mechanism discussed in this paper may not have been isolated without this technique. The device of interest is a mixed signal integrated circuit that provides a digital up-convert function and quadrature modulation. The majority of the circuit functions are digital and as such the majority of the die area is digital. For this analysis, Built In Self Test (BIST) circuitry, an evaluation board for bench testing and FIB techniques were used to successfully identify an unusual failure mechanism. Samples were subjected to Highly Accelerated Stress Test (HAST) as part of the device qualification effort. Post-HAST electrical testing at 200MHz indicated that two units were non-functional. Several different functional blocks on the chip failed electrical testing. One part of the circuitry that failed was the serial interface. The failure analysis team decided to look at the serial interface failure mode first because of the simplicity of the test. After thorough analysis the FA team discovered increasing the data setup time at the serial port input allowed the device to work properly. SEM and FIB techniques were performed which identified a high impedance connection between a metal layer and the underlying via layer. The circuit was modified using a FIB edit, after which all vectors were read back correctly, without the additional set-up time.

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Diagnostic Fault Simulation for the Failure Analyst

ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2004p0181 ◽

2004 ◽

Author(s):

Dan Bodoh ◽

Anthony Blakely ◽

Terry Garyet

Keyword(s):

Fault Diagnosis ◽

Failure Analysis ◽

Complete Solution ◽

Fault Simulation ◽

Building Blocks ◽

Physical World ◽

Design For Test ◽

Fault Diagnosis System ◽

Diagnosis Algorithm ◽

Diagnosis Tool

Abstract Since failure analysis (FA) tools originated in the design-for-test (DFT) realm, most have abstractions that reflect a designer's viewpoint. These abstractions prevent easy application of diagnosis results in the physical world of the FA lab. This article presents a fault diagnosis system, DFS/FA, which bridges the DFT and FA worlds. First, it describes the motivation for building DFS/FA and how it is an improvement over off-the-shelf tools and explains the DFS/FA building blocks on which the diagnosis tool depends. The article then discusses the diagnosis algorithm in detail and provides an overview of some of the supporting tools that make DFS/FA a complete solution for FA. It also presents a FA example where DFS/FA has been applied. The example demonstrates how the consideration of physical proximity improves the accuracy without sacrificing precision.

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Monolithic Module Design and Behavior Improvement of Large Area Dye-sensitized Solar Cell

Journal of Inorganic Materials ◽

10.3724/sp.j.1077.2011.01261 ◽

2011 ◽

Vol 26 (12) ◽

pp. 1261-1265 ◽

Cited By ~ 1

Author(s):

Hui MA ◽

Zhi-Yong LIU ◽

Yu-Ming LU ◽

Xiao-Yan JIN ◽

Chuan-Bing CAI

Keyword(s):

Solar Cell ◽

Dye Sensitized Solar Cell ◽

Large Area ◽

Module Design ◽

Dye Sensitized ◽

And Behavior

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Physical connection [design-for-test]

Electronic Systems and Software ◽

10.1049/ess:20050401 ◽

2005 ◽

Vol 3 (4) ◽

pp. 10-14

Author(s):

C. Edwards

Keyword(s):

Design For Test ◽

Physical Connection ◽

Connection Design

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Study on Common Ground Testing Platform Technology for Telemetry Core Equipment

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.220-223.1472 ◽

2012 ◽

Vol 220-223 ◽

pp. 1472-1475

Author(s):

Qiu Lin Tan ◽

Xiang Dong Pei ◽

Si Min Zhu ◽

Ji Jun Xiong

Keyword(s):

Data Exchange ◽

Common Ground ◽

Digital Signal ◽

Test System ◽

Automatic Test System ◽

Module Design ◽

The Status ◽

Output Module ◽

And Performance ◽

Hardware Circuit

On the basis of automatic test system of the status in domestic and foreign, by analysis of the various functions and performance of the integrated test system, a design of the integrated test system is proposed, FPGA as the core logic controller of the hardware circuit. The system of the hardware design include: digital signal source output modules, analog output module and PCM codec module. Design of hardware circuit are mainly described. In addition, a detailed analysis of some key technologies in the design process was given. Overall, its data exchange with host computer is through the PCI card, data link and bandwidth can be expanded in accordance with the actual needs. The entire system designed in the modular principle, which has a strong scalability.

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