Physical connection [design-for-test]

2005 ◽  
Vol 3 (4) ◽  
pp. 10-14
Author(s):  
C. Edwards
Keyword(s):  
Design For Test ◽  
Physical Connection ◽  
Connection Design

Investigation of High Frequency Failures on a 0.35μm CMOS IC

1999 ◽  
Author(s):  
Alan Kennen ◽  
John F. Guravage ◽  
Lauren Foster ◽  
John Kornblum
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Integrated Circuit ◽  
Metal Layer ◽  
Ion Beam ◽  
Stress Test ◽  
Design For Test ◽  
Interface Failure ◽  
Serial Interface ◽  
High Impedance

Abstract Rapidly changing technology highlights the necessity of developing new failure analysis methodologies. This paper will discuss the combination of two techniques, Design for Test (DFT) and Focused Ion Beam (FIB) analysis, as a means for successfully isolating and identifying a series of high impedance failure sites in a 0.35 μm CMOS design. Although DFT was designed for production testing, the failure mechanism discussed in this paper may not have been isolated without this technique. The device of interest is a mixed signal integrated circuit that provides a digital up-convert function and quadrature modulation. The majority of the circuit functions are digital and as such the majority of the die area is digital. For this analysis, Built In Self Test (BIST) circuitry, an evaluation board for bench testing and FIB techniques were used to successfully identify an unusual failure mechanism. Samples were subjected to Highly Accelerated Stress Test (HAST) as part of the device qualification effort. Post-HAST electrical testing at 200MHz indicated that two units were non-functional. Several different functional blocks on the chip failed electrical testing. One part of the circuitry that failed was the serial interface. The failure analysis team decided to look at the serial interface failure mode first because of the simplicity of the test. After thorough analysis the FA team discovered increasing the data setup time at the serial port input allowed the device to work properly. SEM and FIB techniques were performed which identified a high impedance connection between a metal layer and the underlying via layer. The circuit was modified using a FIB edit, after which all vectors were read back correctly, without the additional set-up time.

Diagnostic Fault Simulation for the Failure Analyst

2004 ◽  
Author(s):  
Dan Bodoh ◽  
Anthony Blakely ◽  
Terry Garyet
Keyword(s):  
Fault Diagnosis ◽  
Failure Analysis ◽  
Complete Solution ◽  
Fault Simulation ◽  
Building Blocks ◽  
Physical World ◽  
Design For Test ◽  
Fault Diagnosis System ◽  
Diagnosis Algorithm ◽  
Diagnosis Tool

Abstract Since failure analysis (FA) tools originated in the design-for-test (DFT) realm, most have abstractions that reflect a designer's viewpoint. These abstractions prevent easy application of diagnosis results in the physical world of the FA lab. This article presents a fault diagnosis system, DFS/FA, which bridges the DFT and FA worlds. First, it describes the motivation for building DFS/FA and how it is an improvement over off-the-shelf tools and explains the DFS/FA building blocks on which the diagnosis tool depends. The article then discusses the diagnosis algorithm in detail and provides an overview of some of the supporting tools that make DFS/FA a complete solution for FA. It also presents a FA example where DFS/FA has been applied. The example demonstrates how the consideration of physical proximity improves the accuracy without sacrificing precision.

Design for Test and Testability

2021 ◽  
pp. 245-264
Author(s):  
Anne Meixner ◽  
Louis J. Gullo
Keyword(s):  
Design For Test

Design for Test and Diagnosis of Power Switches

2015 ◽  
Vol 25 (03) ◽  
pp. 1640013
Author(s):  
Miroslav Valka ◽  
Alberto Bosio ◽  
Luigi Dilillo ◽  
Patrick Girard ◽  
Arnaud Virazel ◽  
...  
Keyword(s):  
Power Consumption ◽  
Industrial Test ◽  
Design For Test ◽  
Power Gating ◽  
Test Quality ◽  
Worst Case ◽  
Manufacturing Defects ◽  
Efficient Test ◽  
Power Switches ◽  
Static Power

Power gating techniques have been adopted so far to reduce the static power consumption of integrated circuits (ICs). Power gating is usually implemented by means of several power switches (PSs). Manufacturing defects affecting PSs can lead to increase in the actual static power consumption and, in the worst case, they can completely isolate a functional block in the IC. Thus, efficient test and diagnosis solutions are needed. In this paper, we present a novel Design for Test and Diagnosis (DfTD) solution able to increase the test quality and diagnosis accuracy of PSs. The proposed approach has been validated through SPICE simulations on ITC’99 benchmark circuits as well as on industrial test cases.

Modular Robot Connection Design

1992 ◽  
Author(s):  
Robert O. Ambrose ◽  
Delbert Tesar
Keyword(s):  
Product Line ◽  
Modular Robots ◽  
Modular Robotics ◽  
Modular Robot ◽  
Manufacturing Costs ◽  
Mechanical Connection ◽  
Automation Equipment ◽  
Connection Design

Abstract The ability to reconfigure automation equipment will reduce the manufacturing costs of obsolesence, training and maintenance while allowing for a faster response to changes in the product line. A modular philosophy will give the user these advantages, but only if based on a common connection standard. A mechanical connection was selected for the UT Modular Robotics Testbed and used in the designs of four robot joint modules and nine robot link modules. The standard was also used for assecories, such as the testand, loading fixtures and endeffectors. Three years of experiments with this connection standard are reviewed, and used as the basis for new connection designs. Experiments using multiple modules assembled as dextrous robots, as well as experiments focusing on the connection itself, will be described. Goals for future connection standards include designs with upward compatibility, combinations of both mechanical and electrical fittings, and robot triendly constraints that allow for automated or remote assembly of modular robots.

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