Digital transmission scheme for ISDB-T and reception characteristics of digital terrestrial television broadcasting system in Japan

Author(s):  
S. Nakahara ◽  
M. Okano ◽  
M. Takada ◽  
T. Kuroda
2021 ◽  
Vol 7 (1) ◽  
pp. 30-32
Author(s):  
Nguyen Huy Hoang ◽  
◽  
Tran Van Nghia ◽  
Le Van Ky ◽  
◽  
...  

Nowadays, with strong development of Science and Technology, integrated circuits continue to dominate not only in the field of digital information. Over the last several years, Technological television industry has taken huge strides and powerful transformation to meet with government’s policy about digitization of television all over the country in period 2015 – 2020. Stemming from the practical needs of “localization of products” and mastering of technological design of DVB-T2 transmitter (Digital Video Broadcasting – Terrestrial for Second generation), the authors have made an effort to research in algorithm, designed and tested in Field Programmable Gate Array (FPGA) technology. DVB-T2 is mainly aimed to replace the current standard DVB-T. The main motivation of DVB-T2 is to provide broadcasters with more advanced and efficient alternative to DVB-T standards. In DVB-T2 transmitter system, digital audio, video, and other data are compressed into a single signal to be transmitted on a single RF channel, using orthogonal frequency-division multiplexing (OFDM) with concatenated channel coding and interleaving. The higher offered bit rate makes it a suited system for carrying HDTV signals on the terrestrial TV channel. The next generation broadcasting systems should be designed to make full use of spectral resources while providing reliable transmissions in order to enable services like multichannel HDTV (High Definition Television) and innovative data casting services. The efficient usage of the radio spectrum can be achieved by the introduction of Single Frequency Networks (SFN). Digital transmitter DVB-T2 implemented on FPGA using a software Xilinx System Generator for DSP tool and Xilinx ISE Design Suite 14.7. System Generator for DSP is in conjunction on environment MATLAB-Simulink that is capable of simulating the proposed hardware structures that is synthesized and implemented by the programmable elements in Field-programmable Gate Arrays. In this project, adaptative MPEG-TS bitrate converter is designed to allows to increasing or reducing the MPEG TS rate by adding or filtering NULL packets. The entire digital transmitter DVB-T2 is integrated in one chip Xilinx FPGA Kintex-7 XC7K325T-1FFG676. Experimental design on development Kit NetFPGA-1G-CML of Digilent Corporation is performed at design department of technology center of Vietnamese Communications Television Development JSC. Authors are continuing to improve products, put into practical applications to replace the digital terrestrial television broadcasting stations that are being used in Vietnam. The article named “Implementation of FPGA-based DVB-T2 transmitter for a second generation digital terrestrial television broadcasting system” presents the research results, design methods, test results to compare, evaluate the accuracy of algorithm implementation. The results open up new directions for technological television in Vietnam.


2021 ◽  
Vol 7 (2) ◽  
pp. 18-21
Author(s):  
Tran Van Nghia ◽  
◽  
Le Van Ky ◽  
Tran Minh Hai ◽  
Le Thi Trang Linh ◽  
...  

This article focus on the implementation of FEC part. The motivation of the design is that FEC is an effective tool to mitigate problems associated with OFDM which stem from multipath fading channel, high speed data rate. One of the key features of BCH codes is that during code design, there is a precise control over the number of symbol errors that are correctable by the code. BCH coder proccesses parralelly with high-speed operation. 8-bit parallel data input and output helps to maximize the throughput. DVB-T2 used LDPC coder, as inner codes with word length up to 64,800 bits, enabling significant proximity to Shannon limit. This encoder supports all code rates and both normal and short frames. Output of LDPC encoder is interleaved with bit interleaver. This project was fully optimized for speed and memory area, fully synchronized by using a single clock. The design was coded in VHDL, synthesized by using Xilinx ISE Design Suite 14.7. The design has been tested on development Kit NetFPGA-1G-CML of Digilent Corporation and the bit map was downloaded into Xilinx Kintex-7 XC7K325T-1FFG676, which is integrated on experimental transmitter system DVB-T2. This research product belong to program “Research of experimental testing of second generation digital terrestrial television broadcasting system DVB-T2” of Vietnamese Communications Television Development JSC.


2014 ◽  
Vol 60 (2) ◽  
pp. 287-290
Author(s):  
Yanfeng Wang ◽  
Dazhi He ◽  
Wenjun Zhang ◽  
Yunfeng Guan ◽  
Yao Wang ◽  
...  

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