EFFICIENT IMPLEMENTATION OF FPGA-BASED FORWARD ERROR CORRECTING COMBINATION AND BIT TO CELL WORD DE-MULTIPLEXER FOR A SECOND GENERATION DIGITAL TERRESTRIAL TELEVISION BROADCASTING SYSTEM

This article focus on the implementation of FEC part. The motivation of the design is that FEC is an effective tool to mitigate problems associated with OFDM which stem from multipath fading channel, high speed data rate. One of the key features of BCH codes is that during code design, there is a precise control over the number of symbol errors that are correctable by the code. BCH coder proccesses parralelly with high-speed operation. 8-bit parallel data input and output helps to maximize the throughput. DVB-T2 used LDPC coder, as inner codes with word length up to 64,800 bits, enabling significant proximity to Shannon limit. This encoder supports all code rates and both normal and short frames. Output of LDPC encoder is interleaved with bit interleaver. This project was fully optimized for speed and memory area, fully synchronized by using a single clock. The design was coded in VHDL, synthesized by using Xilinx ISE Design Suite 14.7. The design has been tested on development Kit NetFPGA-1G-CML of Digilent Corporation and the bit map was downloaded into Xilinx Kintex-7 XC7K325T-1FFG676, which is integrated on experimental transmitter system DVB-T2. This research product belong to program “Research of experimental testing of second generation digital terrestrial television broadcasting system DVB-T2” of Vietnamese Communications Television Development JSC.