Optimization of test time and fault grading of functional test vectors using fault simulation flow

2014 ◽  
Author(s):  
S. Praveen ◽  
Siva Yellampalli ◽  
Ashish Kothari
Keyword(s):  
Fault Simulation ◽  
Functional Test ◽  
Test Time ◽  
Test Vectors ◽  
Fault Grading

SoC Test Data Compression Technique Based on RLE-G

2010 ◽  
Vol 439-440 ◽  
pp. 1595-1600
Author(s):  
Chun Jian Deng ◽  
Liu Wei ◽  
Xi Feng Zheng ◽  
Liang Yang
Keyword(s):  
Data Compression ◽  
Test Data ◽  
Test Time ◽  
Test Data Compression ◽  
Compression Technique ◽  
Current Test ◽  
Soc Test ◽  
Efficient Test ◽  
Data Volume ◽  
Test Vectors

Test data compression has been an effective way to reduce test data volume and test time, as well as to solve automatic test equipment (ATE) memory and bandwidth limitation. We analyze the limitations of current test data compression algorithm and draw on the previous experience to deduce an optimal compression coding model suitable for SoC test data. In addition, in this paper we make full use of the relevance of the test vectors and the advantages of statistical coding to present an efficient test data compression method RLE-G based on the coding model, and give the RLE-G the optimal compression efficiency of the boundary conditions and realization steps. The experimental results for ISCAS 89 benchmark circuits demonstrate RLE-G have the excellent advantages of high compression ratio.

scholarly journals Implementation of a Parallel Fault Simulation System using PODEM in a Hardware Accelerator using Python

2021 ◽  
Vol 23 (06) ◽  
pp. 530-536
Author(s):  
Mahesh Bhat K ◽  
◽  
Namita Palecha ◽  
Keyword(s):  
Test Pattern ◽  
Fault Simulation ◽  
Pattern Generator ◽  
Channel Length ◽  
Simulation System ◽  
Hardware Accelerator ◽  
Vlsi Testing ◽  
Automatic Test Pattern Generator ◽  
Test Vectors ◽  
Input Test

VLSI Testing is one of the essential domains in recent times. With the channel length of the transistor decreasing continually, the number of transistors in a chip increases, thus increasing the probability of defects or faults. Automatic Test Pattern Generator is one way to find such input test vectors to the circuit, which will help identify the faults if present. PODEM algorithm is one such algorithm used in this regard. This paper helps in reducing the runtime of this algorithm by the parallelism approach. Different stuck-at faults in the gate level circuit are simulated parallelly.

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