Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).
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Non-scan design for testability based on fault oriented conflict analysis

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02). ◽

10.1109/ats.2002.1181691 ◽

2003 ◽

Author(s):

Dong Xiang ◽

Shan Gu ◽

Hideo Fujiwara

Keyword(s):

Design For Testability ◽

Conflict Analysis ◽

Scan Design

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Recent advances in test planning for modular testing of core-based SOCs

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02). ◽

10.1109/ats.2002.1181731 ◽

2003 ◽

Cited By ~ 13

Author(s):

V. Iyengar ◽

K. Chakrabarty ◽

E.J. Marinissen

Keyword(s):

Test Planning ◽

Recent Advances ◽

Modular Testing

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Hierarchical fault simulation using behavioral and gate level hardware models

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02). ◽

10.1109/ats.2002.1181740 ◽

2003 ◽

Cited By ~ 7

Author(s):

S. Mirkhani ◽

M. Lavasani ◽

Z. Navabi

Keyword(s):

Fault Simulation

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A high performance IDDQ testable cache for scaled CMOS technologies

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02). ◽

10.1109/ats.2002.1181704 ◽

2003 ◽

Cited By ~ 6

Author(s):

S. Bhunia ◽

Hai Li ◽

K. Roy

Keyword(s):

High Performance ◽

Scaled Cmos

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A state reduction method for non-scan based FSM testing with don't care inputs identification technique

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02). ◽

10.1109/ats.2002.1181685 ◽

2003 ◽

Cited By ~ 2

Author(s):

T. Hosokawa ◽

H. Date ◽

M. Muraoka

Keyword(s):

Reduction Method ◽

State Reduction ◽

Identification Technique

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Statistical analysis of time series data on the number of faults detected by software testing

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02). ◽

10.1109/ats.2002.1181723 ◽

2003 ◽

Cited By ~ 1

Author(s):

S. Amasaki ◽

T. Yoshitomi ◽

O. Mizuno ◽

T. Kikuno ◽

Y. Takagi

Keyword(s):

Time Series ◽

Statistical Analysis ◽

Software Testing ◽

Time Series Data ◽

Series Data ◽

Analysis Of Time Series

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On-chip tap-delay measurements for a digital delay-line used in high-speed inter-chip data communications

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02). ◽

10.1109/ats.2002.1181698 ◽

2003 ◽

Cited By ~ 6

Author(s):

O. Petre ◽

H.G. Kerkhoff

Keyword(s):

High Speed ◽

Delay Line ◽

Data Communications ◽

Chip Data ◽

On Chip

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Test requirement analysis for low cost hierarchical test path construction

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02). ◽

10.1109/ats.2002.1181700 ◽

2003 ◽

Cited By ~ 1

Author(s):

Y. Makris ◽

A. Orailoglu

Keyword(s):

Low Cost ◽

Requirement Analysis

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A partitioning and storage based built-in test pattern generation method for delay faults in scan circuits

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02). ◽

10.1109/ats.2002.1181696 ◽

2003 ◽

Cited By ~ 1

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Delay Faults ◽

Scan Circuits ◽

And Storage

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A simple wrapped core linking module for SoC test access

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02). ◽

10.1109/ats.2002.1181735 ◽

2003 ◽

Author(s):

Jaehoon Song ◽

Sungju Park

Keyword(s):

Soc Test

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Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Non-scan design for testability based on fault oriented conflict analysis

Recent advances in test planning for modular testing of core-based SOCs

Hierarchical fault simulation using behavioral and gate level hardware models

A high performance IDDQ testable cache for scaled CMOS technologies

A state reduction method for non-scan based FSM testing with don't care inputs identification technique

Statistical analysis of time series data on the number of faults detected by software testing

On-chip tap-delay measurements for a digital delay-line used in high-speed inter-chip data communications

Test requirement analysis for low cost hierarchical test path construction

A partitioning and storage based built-in test pattern generation method for delay faults in scan circuits

A simple wrapped core linking module for SoC test access

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).
Latest Publications