Analysis of Through Silicon Vias and substrate coupling in 3D CMOS circuits by Spice simulations

2021 ◽  
Author(s):  
Mohamed el Amine Benkechkache ◽  
Saida Latreche ◽  
Lamis Ghoualmi
Keyword(s):  
Cmos Circuits ◽  
Through Silicon Vias ◽  
Substrate Coupling ◽  
Silicon Vias

scholarly journals Wire-bonded through-silicon vias with low capacitive substrate coupling

2011 ◽  
Vol 21 (8) ◽  
pp. 085035 ◽  
Author(s):  
A C Fischer ◽  
M Grange ◽  
N Roxhed ◽  
R Weerasekera ◽  
D Pamunuwa ◽  
...  
Keyword(s):  
Through Silicon Vias ◽  
Substrate Coupling ◽  
Silicon Vias

Failure and Stress Analysis of Cu TSVs Using GHz-Scanning Acoustic Microscopy and Scanning Infrared Polariscopy

2015 ◽  
Author(s):  
Ingrid De Wolf ◽  
Ahmad Khaled ◽  
Martin Herms ◽  
Matthias Wagner ◽  
Tatjana Djuric ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Stress Analysis ◽  
Rayleigh Waves ◽  
Acoustic Microscopy ◽  
Scanning Acoustic Microscopy ◽  
Through Silicon Vias ◽  
Stress Anisotropy ◽  
Silicon Vias ◽  
Ic Technology ◽  
Detection Of Defects

Abstract This paper discusses the application of two different techniques for failure analysis of Cu through-silicon vias (TSVs), used in 3D stacked-IC technology. The first technique is GHz Scanning Acoustic Microscopy (GHz- SAM), which not only allows detection of defects like voids, cracks and delamination, but also the visualization of Rayleigh waves. GHz-SAM can provide information on voids, delamination and possibly stress near the TSVs. The second is a reflection-based photoelastic technique (SIREX), which is shown to be very sensitive to stress anisotropy in the Si near TSVs and as such also to any defect affecting this stress, such as delamination and large voids.

scholarly journals Resistive Programmable Through-Silicon Vias for Reconfigurable 3-D Fabrics

2012 ◽  
Vol 11 (1) ◽  
pp. 8-11 ◽  
Author(s):  
Davide Sacchetto ◽  
Michael Zervas ◽  
Yuksel Temiz ◽  
Giovanni De Micheli ◽  
Yusuf Leblebici
Keyword(s):  
Through Silicon Vias ◽  
Silicon Vias
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