A survey of FPGA placement algorithm research

2017 ◽  
Author(s):  
Wuqi Wang ◽  
Qingsong Meng ◽  
Zhiwei Zhang
Keyword(s):  
Fpga Placement ◽  
Placement Algorithm

scholarly journals A Sea-of-Gates Style FPGA Placement Algorithm

VLSI Design ◽  
1996 ◽  
Vol 4 (4) ◽  
pp. 293-307
Author(s):  
Kalapi Roy ◽  
Bingzhong (David) Guan ◽  
Carl Sechen
Keyword(s):  
Chip Area ◽  
Field Programmable ◽  
Fpga Placement ◽  
Programmable Gate Arrays ◽  
Placement Algorithm ◽  
Two Phases ◽  
Fixed Cell ◽  
Flexible Architectures ◽  
Design Style ◽  
Global Placement

Field Programmable Gate Arrays (FPGAs) have a pre-defined chip boundary with fixed cell locations and routing resources. Placement objectives for flexible architectures (e.g., the standard cell design style) such as minimization of chip area do not reflect the primary placement goals for FPGAs. For FPGAs, the layout tools must seek 100% routability within the architectural constraints. Routability and congestion estimates must be made directly based on the demand and availability of routing resources for detailed routing of the particular FPGA. We. present a hierarchical placement approach consisting of two phases: a global placement phase followed by a detailed placement phase. The global placement phase minimizes congestion estimates of the global routing regions and satisfies all constraints at a coarser level. The detailed placer seeks to maximize the routability of the FPGA by considering factors which cause congestion at the detailed routing level and to precisely satisfy all of the constraints. Despite having limited knowledge about the gate level architectural details, we have achieved a 90%reduction in the number of unrouted nets in comparison to an industrial tool (the only other tool) developed specifically for this architecture.

scholarly journals Speeding Up FPGA Placement via Partitioning and Multithreading

2009 ◽  
Vol 2009 ◽  
pp. 1-9 ◽  
Author(s):  
Cristinel Ababei
Keyword(s):  
Routing Algorithms ◽  
Design Flow ◽  
Wire Length ◽  
Fpga Design ◽  
Circuit Delay ◽  
Hybrid Parallelization ◽  
Multiple Cores ◽  
Fpga Placement ◽  
Placement And Routing ◽  
Placement Algorithm

One of the current main challenges of the FPGA design flow is the long processing time of the placement and routing algorithms. In this paper, we propose a hybrid parallelization technique of the simulated annealing-based placement algorithm of VPR developed in the work of Betz and Rose (1997). The proposed technique uses balanced region-based partitioning and multithreading. In the first step of this approach placement subproblems are created by partitioning and then processed concurrently by multiple worker threads that are run on multiple cores of the same processor. Our main goal is to investigate the speedup that can be achieved with this simple approach compared to previous approaches that were based on distributed computing. The new hybrid parallel placement algorithm achieves an average speedup of2.5×using four worker threads, while the total wire length and circuit delay after routing are minimally degraded.

scholarly journals Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation

VLSI Design ◽  
1996 ◽  
Vol 4 (4) ◽  
pp. 345-355 ◽  
Author(s):  
Srilata Raman ◽  
C. L. Liu ◽  
Larry G. Jones
Keyword(s):  
Industrial Test ◽  
Timing Constraints ◽  
Relative Location ◽  
Logic Block ◽  
Maximum Delay ◽  
Assignment Algorithm ◽  
Slot Assignment ◽  
Fpga Placement ◽  
Fpga Chip ◽  
Placement Algorithm

In this paper we present a simple but efficient timing-driven placement algorithm for FPGAs. The algorithm computes forces acting on a logic block in the FPGA to determine its relative location with respect to other blocks. The forces depend on the criticality of nets shared between the two blocks. Unlike other net-based approaches, timing constraints are incorporated directly into the force equations to guide the placement. Slot assignment is then used to move the blocks into valid slot locations on the FPGA chip. The assignment algorithm also makes use of the delay information of nets so that the final placement is able to meet the timing criteria specified for the circuit. The novelty of the approach lies in the formulation of the force equations and the manner in which weights of the nets are dynamically altered to influence the placement. Experiments conducted on industrial test circuits and MCNC circuits give very promising results and indicate that the algorithm succeeds in significantly reducing the maximum delay in the circuit. In addition, routability is not adversely affected and running time is low.

Three-Dimensional Physical Design Flow for Monolithic 3D-FPGAs to Improve Timing Closure and Chip Area

2017 ◽  
Vol 26 (10) ◽  
pp. 1750154 ◽  
Author(s):  
Armin Belghadr ◽  
Ali Jahanian
Keyword(s):  
Integrated Circuits ◽  
Semiconductor Industry ◽  
Three Dimensional ◽  
Design Flow ◽  
Chip Area ◽  
Monolithically Integrated ◽  
Timing Closure ◽  
Field Programmable ◽  
Fpga Placement ◽  
Placement Algorithm

By scaling the semiconductor industry to nano-scale era, design and prototyping cost of cell-based Application-Specific Integrated Circuits (ASICs) becomes more expensive and it makes Field Programmable Gate Arrays (FPGAs) more popular among designers. However, there is a gap between FPGAs and ASICs in terms of timing, dynamic power consumption and logic density. Three-dimensional integration, particularly in the full monolithic process, has been considered as a promising solution to reduce the performance gap of ASICs and FPGAs. In this paper, two new architectures for the monolithically integrated 3D-FPGAs are introduced. In order to exploit the great potentials of the suggested architectures, a new three-dimensional FPGA placement algorithm is proposed thereafter. The proposed placement algorithm, named JABE, is the first of its kind that enables designers to take advantages of the large number of vertical interconnections in the monolithically stacked 3D-FPGAs. Our experiments show a 24% timing improvement for the new architectures and CAD algorithms compared with the conventional TSV-based 3D-FPGAs and design flows. In addition, improvements in terms of the total wirelength and area footprint are reported for the proposed placement algorithms and new architectures.

Sign in / Sign up

Export Citation Format

Share Document