High-fidelity quantum gates for OAM single qudits on quantum memory

The application of high-dimensional quantum systems (qudits) in quantum computing and communications seems to be a promising avenue due to the possibility of increasing the amount of information encoded in one physical carrier. In this work, we propose a method for implementing single-qudit gates for qudits based on light modes with orbital angular momentum (OAM). Method for logical qudits encoding, which ensures the quasi-cyclicity of operations, is introduced. Based on the protocol for converting the OAM of light in the Raman quantum memory scheme (Vashukevich et al 2020 Phys. Rev. A 101 033830), we show that the considered gates provide an extremely high level of fidelity of single-qudit transformations. We also compare quantum gates’ properties for systems of different dimensions and find the optimal conditions for carrying out transformations in the protocol under consideration.

Preliminary demonstration of a persistent Josephson phase-slip memory cell with topological protection

Superconducting computing promises enhanced computational power in both classical and quantum approaches. Yet, scalable and fast superconducting memories are not implemented. Here, we propose a fully superconducting memory cell based on the hysteretic phase-slip transition existing in long aluminum nanowire Josephson junctions. Embraced by a superconducting ring, the memory cell codifies the logic state in the direction of the circulating persistent current, as commonly defined in flux-based superconducting memories. But, unlike the latter, the hysteresis here is a consequence of the phase-slip occurring in the long weak link and associated to the topological transition of its superconducting gap. This disentangles our memory scheme from the large-inductance constraint, thus enabling its miniaturization. Moreover, the strong activation energy for phase-slip nucleation provides a robust topological protection against stochastic phase-slips and magnetic-flux noise. These properties make the Josephson phase-slip memory a promising solution for advanced superconducting classical logic architectures or flux qubits.

Reduced Area and Low Power Implementation of FFT/IFFT Processor

The Fast Fourier Transform (FFT) and Inverse FFT(IFFT) are used in most of the digital signal processing applications. Real time implementation of FFT/IFFT is required in many of these applications. In this paper, an FPGA reconfigurable fixed point implementation of FFT/IFFT is presented. A manually VHDL codes are written to model the proposed FFT/IFFT processor. Two CORDIC-based FFT/IFFT processors based on radix-2and radix-4 architecture are designed. They have one butterfly processing unit. An efficient In-place memory assignment and addressing for the shared memory of FFT/IFFT processors are proposed to reduce the complexity of memory scheme. With "in-place" strategy, the outputs of butterfly operation are stored back to the same memory location of the inputs. Because of using DIF FFT, the output was to be in reverse order. To solve this issue, we have re-use the block RAM that used for storing the input sample as reordering unit to reduce hardware cost of the proposed processor. The Spartan-3E FPGA of 500,000 gates is employed to synthesize and implement the proposed architecture. The CORDIC based processors can save 40% of power consumption as compared with Xilinx logic core architectures of system generator.