Edge Computing-based Defect Identification Model of Power IoT Edge Side Devices

2020 ◽  
Author(s):  
Dawei Li ◽  
Gengtao Jia ◽  
Chunhe Song ◽  
Shimao Yu
Keyword(s):  
Edge Computing ◽  
Defect Identification ◽  
Edge Side ◽  
Identification Model

scholarly journals A variable-level automated defect identification model based on machine learning

2019 ◽  
Vol 24 (2) ◽  
pp. 1045-1061 ◽  
Author(s):  
Yuwei Zhang ◽  
Ying Xing ◽  
Yunzhan Gong ◽  
Dahai Jin ◽  
Honghui Li ◽  
...  
Keyword(s):  
Machine Learning ◽  
Defect Identification ◽  
Model Based ◽  
Variable Level ◽  
Identification Model

Smart Community Edge: Stream Processing Edge Computing Node for Smart Community Services

2020 ◽  
Vol 140 (9) ◽  
pp. 1030-1039
Author(s):  
W.A. Shanaka P. Abeysiriwardhana ◽  
Janaka L. Wijekoon ◽  
Hiroaki Nishi
Keyword(s):  
Stream Processing ◽  
Community Services ◽  
Edge Computing ◽  
Computing Node ◽  
Smart Community

Load Balancing for Energy-Harvesting Mobile Edge Computing

2021 ◽  
Vol E104.A (1) ◽  
pp. 336-342
Author(s):  
Ping ZHAO ◽  
Jiawei TAO ◽  
Abdul RAUF ◽  
Fengde JIA ◽  
Longting XU
Keyword(s):  
Energy Harvesting ◽  
Load Balancing ◽  
Edge Computing ◽  
Mobile Edge Computing

Dynamic Service Placement and Load Distribution in Edge Computing

2020 ◽  
Author(s):  
Adyson Magalhaes Maia ◽  
Yacine Ghamri-Doudane ◽  
Dario Vieira ◽  
Miguel Franklin de Castro
Keyword(s):  
Load Distribution ◽  
Edge Computing ◽  
Service Placement

Systematic Defect Identification through Layout Snippet Clustering

2010 ◽  
Author(s):  
Wing Chiu Tam ◽  
Osei Poku ◽  
R. D. (Shawn) Blanton
Keyword(s):  
Design Process ◽  
Integrated Circuit ◽  
Yield Loss ◽  
Defect Identification ◽  
Clustering Techniques ◽  
Dominant Component

Abstract Systematic defects due to design-process interactions are a dominant component of integrated circuit (IC) yield loss in nano-scaled technologies. Test structures do not adequately represent the product in terms of feature diversity and feature volume, and therefore are unable to identify all the systematic defects that affect the product. This paper describes a method that uses diagnosis to identify layout features that do not yield as expected. Specifically, clustering techniques are applied to layout snippets of diagnosis-implicated regions from (ideally) a statistically-significant number of IC failures for identifying feature commonalties. Experiments involving an industrial chip demonstrate the identification of possible systematic yield loss due to lithographic hotspots.

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