A 40 Gbps PAM-4 Receiver with 12-Tap Direct Decision Feedback Equalizer Employing 1.5-stage Slicers in 65-nm CMOS
2017 ◽
Vol E100.B
(3)
◽
pp. 433-439
◽
2014 ◽
Vol 9
(9th)
◽
pp. 1-12
2018 ◽
Vol E101.A
(11)
◽
pp. 1949-1951
2005 ◽
Vol 30
(4)
◽
pp. 865-880
◽
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