Leakage current in high density CCD memory structures

Abstract A novel electrical screening method of channel hole bending (ChB) defects is proposed for the implementation of high-density vertical NAND (VNAND) flash memory. The ChB defects induces the leakage current between the two adjacent channel holes, which leads to fatal failure in storage systems. Thus, it is one of the key requirements for VNAND mass production to screen ChB defects electrically in advance. In the proposed screening method, a 3D checkerboard (CKBD) pattern is introduced, which consists of alternating programed (‘0’) and inhibited (‘1’) memory cells in a diagonal and horizontal direction. By measuring the leakage current between the channel holes, ChB defects can be successfully detected electrically.

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High density and low leakage current based SRAM cell using 45 nm technology

International Journal of Electronics ◽

10.1080/00207217.2012.713023 ◽

2013 ◽

Vol 100 (4) ◽

pp. 536-552 ◽

Cited By ~ 5

Author(s):

Shyam Akashe ◽

Sanjay Sharma

Keyword(s):

Leakage Current ◽

High Density ◽

Low Leakage ◽

Low Leakage Current ◽

Sram Cell

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The Characterization of Defect States Responsible for Leakage Current in Tantalum Pentoxide Films for Very High Density DRAM Applications

10.7567/ssdm.1994.c-7-4 ◽

1994 ◽

Cited By ~ 1

Author(s):

W. S. Lau ◽

T. S. Tan ◽

N. P. Sandler ◽

B. S. Page

Keyword(s):

Leakage Current ◽

High Density ◽

Tantalum Pentoxide ◽

Defect States ◽

Very High

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Optimization of PVD Ti/CVD TiN Liner for 0.35 μm Tungsten Plug Technology

MRS Proceedings ◽

10.1557/proc-427-383 ◽

1996 ◽

Vol 427 ◽

Author(s):

C.-K. Wang ◽

L. M. Liu ◽

D. M. Liao ◽

D. C. Smith ◽

M. Danek

Keyword(s):

Contact Resistance ◽

Leakage Current ◽

Threshold Voltage ◽

High Density ◽

Rf Power ◽

Plasma Enhanced Cvd ◽

Device Application ◽

Process Variants ◽

Major Process ◽

Density Plasma

AbstractA novel plasma enhanced CVD TiN process was integrated with high density plasma sputter etch preclean (PCII) and 1:1.5 collimated PVD Ti (c-PVD Ti) process to deposit a Ti/TiN liner for tungsten contact and via plugs. The integrated liner process was optimized for a 0.35 μm nonsalicide CMOS device application. RF power and sputter depth used for contact preclean were the major process variants affecting the contact resistance, junction leakage and transistor threshold voltage. Low contact resistance was obtained for a c-PVD Ti thickness of ∼375 Å. Via resistance was significantly lower with c-PVD Ti/CVD TiN liner as compared to only a TiN liner. Contact resistance for c-PVD Ti/c-PVD TiN and c-PVD Ti/CVD TiN liners were comparable while contacts with conventional PVD Ti/TiN liner showed significantly higher values due to poor step coverage. Low junction leakage current was obtained for integrated c- PVD Ti/CVD TiN stack.

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