A novel 4.6F/sup 2/ NOR cell technology with lightly doped source (LDS) junction for high density flash memories

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217) ◽

10.1109/iedm.1998.746518 ◽

2002 ◽

Author(s):

Jonghan Kim ◽

Jeong-Hyuk Choi ◽

Yong-Ju Choi ◽

Hun-Kyu Lee ◽

Kyeong-Tae Kim ◽

...

Keyword(s):

High Density ◽

Flash Memories ◽

Cell Technology

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Novel 0.44 μm/sup 2/ Ti-salicide STI cell technology for high-density NOR flash memories and high performance embedded application

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217) ◽

10.1109/iedm.1998.746517 ◽

2002 ◽

Author(s):

H. Watanabe ◽

S. Yamada ◽

M. Tanimoto ◽

M. Matsui ◽

S. Kitamura ◽

...

Keyword(s):

High Performance ◽

High Density ◽

Flash Memories ◽

Cell Technology ◽

Embedded Application ◽

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A novel high-density 5F/sup 2/ NAND STI cell technology suitable for 256 Mbit and 1 Gbit flash memories

International Electron Devices Meeting. IEDM Technical Digest ◽

10.1109/iedm.1997.650379 ◽

2002 ◽

Author(s):

K. Shimizu ◽

K. Narita ◽

H. Watanabe ◽

E. Kamiya ◽

Y. Takeuchi ◽

...

Keyword(s):

High Density ◽

Flash Memories ◽

Cell Technology

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Comparison of TID Response of Micron Technology Single-Level Cell High Density NAND Flash Memories

2010 IEEE Radiation Effects Data Workshop ◽

10.1109/redw.2010.5619508 ◽

2010 ◽

Author(s):

Duc N. Nguyen ◽

Farokh Irom

Keyword(s):

High Density ◽

Flash Memories ◽

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Invalid Data-Aware Coding to Enhance the Read Performance of High-Density Flash Memories

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) ◽

10.1109/micro.2018.00046 ◽

2018 ◽

Author(s):

Wonil Choi ◽

Myoungsoo Jung ◽

Mahmut Kandemir

Keyword(s):

High Density ◽

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A novel NVRAM cell technology for high density applications

10.1109/iedm.1988.32844 ◽

2003 ◽

Author(s):

Y. Yasmauchi ◽

K. Tanaka ◽

K. Sakiyama

Keyword(s):

High Density ◽

Cell Technology

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High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2002.803045 ◽

2002 ◽

Vol 37 (10) ◽

pp. 1318-1325 ◽

Author(s):

T. Tanzawa ◽

Y. Takano ◽

K. Watanabe ◽

S. Atsumi

Keyword(s):

High Voltage ◽

High Density ◽

Flash Memories ◽

Circuit Techniques ◽

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Double-sided rugged poly Si FIN STC (stacked capacitor cell) technology for high density DRAMs

10.1109/drc.1994.1009413 ◽

2005 ◽

Author(s):

H. Ogihara ◽

M. Yoshimaru ◽

S. Takase ◽

H. Kurogi ◽

H. Tamura ◽

...

Keyword(s):

High Density ◽

Cell Technology ◽

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Design Principles of Dielectric Layers for High Density Flash Memories

ECS Meeting Abstracts ◽

10.1149/ma2019-02/13/875 ◽

2019 ◽

Keyword(s):

Design Principles ◽

High Density ◽

Flash Memories ◽

Dielectric Layers

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Ag Ionic Memory Cell Technology for Terabit-Scale High-Density Application

2019 Symposium on VLSI Technology ◽

10.23919/vlsit.2019.8776568 ◽

2019 ◽

Author(s):

Shosuke Fujii ◽

Reika Ichihara ◽

Takuya Konno ◽

Marina Yamaguchi ◽

Harumi Seki ◽

...

Keyword(s):

Memory Cell ◽

High Density ◽

Cell Technology

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A Quick Boosting Charge Pump Circuit for High Density and Low Voltage Flash Memories

Proceedings of 1994 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.1994.586217 ◽

2005 ◽

Author(s):

T. Tanzawa ◽

Y. Tanaka ◽

T. Tanaka ◽

H. Nakamura ◽

H. Oodaira ◽

...

Keyword(s):

Low Voltage ◽

Charge Pump ◽

High Density ◽

Flash Memories ◽

Charge Pump Circuit

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