Optimization of Charge Pump Based on Piecewise Modeling of Output-Voltage Ripple

This work proposes a piecewise modeling of output-voltage ripple for linear charge pumps. The proposed modeling can obtain a more accurate design expression of power-conversion efficiency. The relationship between flying and output capacitance, as well as switching frequency and optimize power-conversion efficiency can be calculated. The proposed modeling is applied to three charge-pump circuits: 1-stage linear charge pump, dual-branch 1-stage linear charge pump and 4× cross-coupled charge pump. Circuit-level simulation is used to verify the accuracy of proposed modeling.

A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM

As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes such as hybrid pump circuit (HCP) and cross-coupled hybrid pump circuits (CHPC) were introduced to improve the pumping efficiency and pump down speed. However, they still suffer from pumping efficiency degradation, low level |VBB|, and small pumping currents at very low VDD. A novel negative charge pump using an enhanced pumping clock is proposed. The proposed cross-coupled charge pump consists of the enhanced pumping clock generator (ECG) having a pair of inverters and PMOS latch circuit to produce an enhanced control signal with a greater amplitude, thereby working efficiently especially at low supply voltages. The proposed scheme is validated with a HSPICE simulation using the TSMC 180 nm process. The proposed scheme can be operated down to VDD = 0.4 V, and |VBB|/VDD is obtained to be 86.1% at VDD = 0.5 V and Cload = 20 nF. Compared to the state-of-the-art CHPC scheme, the pumping efficiency is larger by 35% at VDD = 0.6 V and RL = 10 KΩ, and the pumping current is 2.17 times greater at VDD = 1.2 V and VBB = 0 V, making the circuit suitable for very low supply voltage applications in DRAMs.

Backscatter Ex-Nihilo: Single-component, Fully-passive Backscattering for Microcontrollers

This paper investigates the harvesting of RF power using the existing electrostatic discharge (ESD) protection circuits of most ICs. Because of the internal diode configuration, a single off-chip capacitor is enough to create a charge pump circuit for rectifying and storing sufficient DC power to passively operate a microcontroller. This paper explores ESD circuitry and shows the feasibility of ESD-based power harvesting. A proof- of-concept device demonstrates a fully-passive backscatter link created using a MSP430. Backscatter communication is achieved through modulation of the internal configuration of a General Purpose Input Output (GPIO) pin on a microcontroller. This type of circuit enables two types of communication: zombie-links in which data is able to be transferred after a device has had its battery removed, as well as a mechanism for hidden identification or verification data, such as chip dielets.