Secure 3D CMOS Chip Stacks with Backside Buried Metal Power Delivery Networks for Distributed Decoupling Capacitance

2020 ◽  
Author(s):  
Hiroki Sonoda ◽  
Kazuki Monta ◽  
Takaaki Okidono ◽  
Yuuki Araga ◽  
Naoya Watanabe ◽  
...  
Keyword(s):  
Power Delivery ◽  
Power Delivery Networks ◽  
Cmos Chip ◽  
Delivery Networks

scholarly journals 3-D CMOS Chip Stacking for Security ICs Featuring Backside Buried Metal Power Delivery Networks With Distributed Capacitance

2021 ◽  
pp. 1-6
Author(s):  
Kazuki Monta ◽  
Hiroki Sonoda ◽  
Takaaki Okidono ◽  
Yuuki Araga ◽  
Naoya Watanabe ◽  
...  
Keyword(s):  
Power Delivery ◽  
Power Delivery Networks ◽  
Cmos Chip ◽  
Delivery Networks

Practical approach to power integrity‐driven design process for power‐delivery networks

2016 ◽  
Vol 10 (5) ◽  
pp. 448-455 ◽  
Author(s):  
Baekseok Ko ◽  
Joowon Kim ◽  
Jaemin Ryoo ◽  
Chulsoon Hwang ◽  
Chan‐Keun Kwon ◽  
...  
Keyword(s):  
Design Process ◽  
Power Delivery ◽  
Practical Approach ◽  
Power Integrity ◽  
Power Delivery Networks ◽  
Delivery Networks

Cooling three-dimensional integrated circuits using power delivery networks

2012 ◽  
Author(s):  
Hai Wei ◽  
Tony F. Wu ◽  
Deepak Sekar ◽  
Brian Cronquist ◽  
Roger Fabian Pease ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Three Dimensional ◽  
Power Delivery ◽  
Power Delivery Networks ◽  
Delivery Networks
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