14nm FinFET process technology platform for over 100M pixel density and ultra low power 3D Stack CMOS Image Sensor

Author(s):  
Donghee Yu ◽  
Jong-Won Choi ◽  
Sangil Jung ◽  
Minho Kwon ◽  
Il-Seon Ha ◽  
...  
2015 ◽  
Vol 50 (10) ◽  
pp. 2419-2430 ◽  
Author(s):  
Numa Couniot ◽  
Guerric de Streel ◽  
Francois Botman ◽  
Angelo Kuti Lusala ◽  
Denis Flandre ◽  
...  

Sensors ◽  
2015 ◽  
Vol 15 (3) ◽  
pp. 5531-5554 ◽  
Author(s):  
Ismail Cevik ◽  
Xiwei Huang ◽  
Hao Yu ◽  
Mei Yan ◽  
Suat Ay

2021 ◽  
Vol 3 (4) ◽  
Author(s):  
S. Chrisben Gladson ◽  
Adith Hari Narayana ◽  
V. Thenmozhi ◽  
M. Bhaskar

AbstractDue to the increased processing data rates, which is required in applications such as fifth-generation (5G) wireless networks, the battery power will discharge rapidly. Hence, there is a need for the design of novel circuit topologies to cater the demand of ultra-low voltage and low power operation. In this paper, a low-noise amplifier (LNA) operating at ultra-low voltage is proposed to address the demands of battery-powered communication devices. The LNA dual shunt peaking and has two modes of operation. In low-power mode (Mode-I), the LNA achieves a high gain ($$S21$$ S 21 ) of 18.87 dB, minimum noise figure ($${NF}_{min.}$$ NF m i n . ) of 2.5 dB in the − 3 dB frequency range of 2.3–2.9 GHz, and third-order intercept point (IIP3) of − 7.9dBm when operating at 0.6 V supply. In high-power mode (Mode-II), the achieved gain, NF, and IIP3 are 21.36 dB, 2.3 dB, and 13.78dBm respectively when operating at 1 V supply. The proposed LNA is implemented in UMC 180 nm CMOS process technology with a core area of $$0.40{\mathrm{ mm}}^{2}$$ 0.40 mm 2 and the post-layout validation is performed using Cadence SpectreRF circuit simulator.


Author(s):  
Bing Zhang ◽  
Congzhen Hu ◽  
Junhua Lai ◽  
Youze Xin ◽  
Zhuoqi Guo ◽  
...  

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