Several CMOS imager sensors were proposed to obtain high dynamic range imager (>100 dB). However, as drawback these imagers implement a large number of transistors per pixel resulting in a low fill factor, high power consumption and high complexity CMOS image sensors. In this work, a new operation mode for 3 T CMOS image sensors is presented for high dynamic range (HDR) applications. The operation mode consists of biasing the conventional reset transistor as active load to photodiode generating a reference current. The output voltage achieves a steady state when the photocurrent becomes equal to the reference current, similar to the inverter operation in the transition region. At a specific bias voltage, the output swings from o to Vdd in a small light intensity range; however, high dynamic range is achieve using multiple readout at different bias voltage. For high dynamic range operation different values of bias voltage can be applied from each one, and the signal can be captured to compose a high dynamic range image. Compared to other high dynamic range architectures this proposed CMOS image pixel show as advantage high fill-factor (3 T) and lower complexity. Moreover, as the CMOS pixel does not operate in integration mode, de readout can be performed at higher speed. A prototype was fabricated at 3.3 V 0.35 µm CMOS technology. Experimental results are shown by applying five different control voltage from 0.65 to 1.2 V is possible to obtain a dynamic range of about 100 dB.
Modelling of high dynamic range logarithmic CMOS image sensors
