Low-power ultra-wideband power detector IC in 130 nm CMOS technology

2012 ◽  
Author(s):  
Xin Yang ◽  
Yorikatsu Uchida ◽  
Qing Liu ◽  
Toshihiko Yoshimasu
Keyword(s):  
Low Power ◽  
Cmos Technology ◽  
Ultra Wideband ◽  
Power Detector

A compact low power ultra wideband impulse generator on 0.18 μM CMOS technology

2011 ◽  
Vol 53 (5) ◽  
pp. 1128-1131
Author(s):  
Ruibing Dong ◽  
Ramesh K. Pokharel ◽  
Haruichi Kanaya ◽  
Keiji Yoshida
Keyword(s):  
Low Power ◽  
Cmos Technology ◽  
Ultra Wideband ◽  
Impulse Generator

scholarly journals A Low-Power Squaring Circuit with Regulated Output and Improved Settling Time in 180 nm CMOS for 3–5 GHz IR-UWB Applications

2021 ◽  
Vol 19 ◽  
pp. 79-84
Author(s):  
Daniel Schrüfer ◽  
Jürgen Röber ◽  
Timo Mai ◽  
Robert Weigel
Keyword(s):  
Transfer Function ◽  
Power Consumption ◽  
Low Power ◽  
Cmos Technology ◽  
Settling Time ◽  
Ultra Wideband ◽  
Quadratic Term ◽  
Slew Rate ◽  
Data Rates ◽  
5 Ghz

Abstract. This paper demonstrates a low-power squaring circuit for 3–5 GHz non-coherent Impulse-Radio Ultra-Wideband (IR-UWB) receivers for Pulse Position Modulation (PPM) in a low-cost 180 nm CMOS technology. The squaring, which is the key element in typical IR-UWB receivers, is performed exploiting the non-linear transfer function of a MOS transistor. For a high gain at low power consumption the transistor is biased in the moderate inversion region, where the second-order derivative of the transconductance gm and, as a result, the quadratic term in the transfer function reaches a maximum. A control loop was implemented to set the dc output voltage to a defined value and thus to allow a comparison of the squarer output signal with a defined threshold voltage, which can easily be set and adjusted (e.g. by a DAC). To speed up the settling time of the output and hence to reach higher data rates, a novel slew-rate booster is implemented at the output. Thereby, the squarer is capable of data rates of up to 15.6 Mbit s−1, which is more than two times higher compared to the circuit without the slew-rate booster, while only consuming 72.4 µW in addition. In the extracted post-layout simulations the whole circuitry consumes 724 µA at a 1.8 V power supply, resulting in a power consumption of 1.3 mW.

A Low-Power Ring Oscillator with Temperature Compensation for IR-UWB Applications

2018 ◽  
Vol 27 (12) ◽  
pp. 1850186 ◽  
Author(s):  
Zied Sakka ◽  
Nadia Gargouri ◽  
Mounir Samet
Keyword(s):  
Monte Carlo ◽  
Low Power ◽  
Temperature Compensation ◽  
Temperature Stability ◽  
Cmos Technology ◽  
Impulse Radio ◽  
Ring Oscillator ◽  
Ultra Wideband ◽  
Center Frequency ◽  
Uwb Applications

This paper presents a 4[Formula: see text]GHz low-power ring oscillator with supply and temperature compensation for use in impulse-radio ultra-wideband (IR-UWB) applications. Simulations using TSMC 0.18[Formula: see text][Formula: see text]m CMOS technology show that this configuration is able to achieve a 94.87% reduction in the variation of the center frequency of the uncompensated VCO and 25[Formula: see text]ppm/[Formula: see text]C temperature stability. Monte Carlo simulations have also been performed, and demonstrate a 3[Formula: see text] deviation of about 7.26%. The power for the proposed circuit is only 4.5[Formula: see text]mW at 27[Formula: see text]C.

CMOS LOW-POWER ANALOGUE BASEBAND CIRCUITS FOR A NON-COHERENT LOW DATA RATE IR-UWB RECEIVER

2011 ◽  
Vol 20 (01) ◽  
pp. 45-55 ◽  
Author(s):  
ZHIMING CHEN ◽  
YUANJIN ZHENG ◽  
XIAOJUN YUAN
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Input Pulse ◽  
Cmos Technology ◽  
Input Power ◽  
Data Rate ◽  
Ultra Wideband ◽  
Received Signal Strength Indicator ◽  
Limiting Amplifier ◽  
Uwb Receiver

A low-power analogue baseband circuit for a low data-rate impulse radio ultra-wideband (IR-UWB) receiver is designed and implemented in a 0.18 μm CMOS technology, including a variable-gain amplifier (VGA), a received signal strength indicator (RSSI), and a limiting amplifier (LA). The VGA has gain range from -9 to 63 dB and bandwidth from 31 to 187 MHz. An input P1dB of -15.4 dBm is achieved at 0 dB gain. The RSSI has a dynamic range of approximately 70 dB. The RSSI linearity error is within ±1.2 dB for an input power from -77.5 dBm to -36.2 dBm. By adjusting the VGA gain and the LA threshold, the LA is able to detect an input pulse as low as 0.6 mV at a data rate of 15 mega-pulse per second (MP/s). The analogue baseband circuit draws current of 6.03 mA from a single voltage supply of 1.8 V. The test chip occupies an area of 970 μm × 750 μm, including two output buffers.

scholarly journals A Novel High Linearity and Low Power Folded CMOS LNA for UWB Receivers

2017 ◽  
Vol 27 (03) ◽  
pp. 1850047
Author(s):  
Xin Zhang ◽  
Chunhua Wang ◽  
Yichuang Sun ◽  
Haijun Peng
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Low Noise ◽  
Ultra Wideband ◽  
Oxide Semiconductor ◽  
High Linearity ◽  
Low Supply Voltage

This paper presents a high linearity and low power Low-Noise Amplifier (LNA) for Ultra-Wideband (UWB) receivers based on CHRT 0.18[Formula: see text][Formula: see text]m Complementary Metal-Oxide-Semiconductor (CMOS) technology. In this work, the folded topology is adopted in order to reduce the supply voltage and power consumption. Moreover, a band-pass LC filter is embedded in the folded-cascode circuit to extend bandwidth. The transconductance nonlinearity has a great impact on the whole LNA linearity performance under a low supply voltage. A post-distortion (PD) technique employing an auxiliary transistor is applied in the transconductance stage to improve the linearity. The post-layout simulation results indicate that the proposed LNA achieves a maximum power gain of 12.8[Formula: see text]dB. The input and output reflection coefficients both are lower than [Formula: see text][Formula: see text]dB over 2.5–11.5[Formula: see text]GHz. The input third-order intercept point (IIP3) is 5.6[Formula: see text]dBm at 8[Formula: see text]GHz and the noise figure (NF) is lower than 4.0[Formula: see text]dB. The LNA consumes 5.4[Formula: see text]mW power under a 1[Formula: see text]V supply voltage.

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