scholarly journals A Low-Power Squaring Circuit with Regulated Output and Improved Settling Time in 180 nm CMOS for 3–5 GHz IR-UWB Applications

2021 ◽  
Vol 19 ◽  
pp. 79-84
Author(s):  
Daniel Schrüfer ◽  
Jürgen Röber ◽  
Timo Mai ◽  
Robert Weigel
Keyword(s):  
Transfer Function ◽  
Power Consumption ◽  
Low Power ◽  
Cmos Technology ◽  
Settling Time ◽  
Ultra Wideband ◽  
Quadratic Term ◽  
Slew Rate ◽  
Data Rates ◽  
5 Ghz

Abstract. This paper demonstrates a low-power squaring circuit for 3–5 GHz non-coherent Impulse-Radio Ultra-Wideband (IR-UWB) receivers for Pulse Position Modulation (PPM) in a low-cost 180 nm CMOS technology. The squaring, which is the key element in typical IR-UWB receivers, is performed exploiting the non-linear transfer function of a MOS transistor. For a high gain at low power consumption the transistor is biased in the moderate inversion region, where the second-order derivative of the transconductance gm and, as a result, the quadratic term in the transfer function reaches a maximum. A control loop was implemented to set the dc output voltage to a defined value and thus to allow a comparison of the squarer output signal with a defined threshold voltage, which can easily be set and adjusted (e.g. by a DAC). To speed up the settling time of the output and hence to reach higher data rates, a novel slew-rate booster is implemented at the output. Thereby, the squarer is capable of data rates of up to 15.6 Mbit s−1, which is more than two times higher compared to the circuit without the slew-rate booster, while only consuming 72.4 µW in addition. In the extracted post-layout simulations the whole circuitry consumes 724 µA at a 1.8 V power supply, resulting in a power consumption of 1.3 mW.

scholarly journals Low power design of ultra wideband PLL using 90 nm CMOS technology

2020 ◽  
Vol 20 (2) ◽  
pp. 727
Author(s):  
Fadhilah Binti Noor Al Amin ◽  
Nabihah Ahmad ◽  
Siti Hawa Ruslan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Large Scale ◽  
Vlsi Design ◽  
Electronic System ◽  
Low Power Design ◽  
Cmos Technology ◽  
Ultra Wideband

<span>The rapid growth of the electronic system has become one of the challenges in the high performance of Very Large Scale Integration (VLSI) design and has contributed to the evolution of Phase Locked Loop (PLL) system design as one of the inevitable and significant necessities in the modern days. This design focus on the development of PLL system that can operate at a high performance within the Ultra-Wideband (UWB) frequency but consume low power that may be useful for future device implementation in the communication system. All proposed sub modules of PLL is highly suitable for low power and high speed application as each of them consumes overall power consumption around 2 µW until 1 mW with frequency from 3.1 GHz to 10.6 GHz. All the design architecture, schematic, simulation and analysis are implemented using Synopsys Tool in 90 nm CMOS technology. Through the overall analysis, it can be concluded that this proposed sub modules design of the PLL system has better performance compared to previous work in terms of power consumption and frequency.</span>

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

scholarly journals A 0.18um CMOS Low Noise Amplifier for 3-5ghz UWB Receivers

2018 ◽  
Vol 7 (3.6) ◽  
pp. 84
Author(s):  
N Malika Begum ◽  
W Yasmeen
Keyword(s):  
Power Supply ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Noise Amplifier ◽  
5 Ghz ◽  
Chebyshev Filter ◽  
Minimum Noise

This paper presents an Ultra-Wideband (UWB) 3-5 GHz Low Noise Amplifier (LNA) employing Chebyshev filter. The LNA has been designed using Cadence 0.18um CMOS technology. Proposed LNA achieves a minimum noise figure of 2.2dB, power gain of 9dB.The power consumption is 6.3mW from 1.8V power supply.  

Design of Low Power Integrated CMOS Potentiometric Biosensor for Direct Electronic Detection of DNA Hybridization

2014 ◽  
Vol 67 (1) ◽  
Author(s):  
Wong How Hwan ◽  
Vinny Lam Siu Fan ◽  
Yusmeeraz Yusof
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Dna Hybridization ◽  
Point Of Care ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Channel Length ◽  
Electrical Signal ◽  
Oxide Semiconductor ◽  
Detection Circuit

The purpose of this research is to design a low power integrated complementary metal oxide semiconductor (CMOS) detection circuit for charge-modulated field-effect transistor (CMFET) and it is used for the detection of deoxyribonucleic acid (DNA) hybridization. With the available CMOS technology, it allows the realization of complete systems which integrate the sensing units and transducing elements in the same device. Point-of-care (POC) testing device is a device that allows anyone to operate anywhere and obtain immediate results. One of the important features of POC device is low power consumption because it is normally battery-operated. The power consumption of the proposed integrated CMOS detection circuit requires only 14.87 mW. The detection circuit will amplify the electrical signal that comes from the CMFET to a specified level in order to improve the recording characteristics of the biosensor. Self-cascode topology was used in the drain follower circuit in order to reduce the channel length modulation effect. The proposed detection circuit was designed with 0.18µm Silterra CMOS fabrication process and simulated under Cadence Simulation Tool. 

A linear, ultra wideband, low-power, 2.1-5 GHz, VCO

2010 ◽  
pp. n/a-n/a ◽  
Author(s):  
Athanasios Tsitouras ◽  
Fotis Plessas ◽  
Grigorios Kalivas
Keyword(s):  
Low Power ◽  
Ultra Wideband ◽  
5 Ghz

A CLOCK GATED SUCCESSIVE APPROXIMATION REGISTER FOR A/D CONVERSIONS

2014 ◽  
Vol 23 (02) ◽  
pp. 1450023
Author(s):  
MOHAMED O. SHAKER ◽  
MAGDY A. BAYOUMI
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
Power Supply ◽  
Cmos Technology ◽  
Clock Signal ◽  
Switching Activity ◽  
Successive Approximation Register ◽  
Simulation Results ◽  
Data Switching

A novel low power clock gated successive approximation register (SAR) is proposed. The new register is based on gating the clock signal when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 8 bits has been designed up to the layout level with 1 V power supply in 90 nm CMOS technology and has been simulated using SPECTRE. Simulation results have shown that the proposed register saves up to 75% of power consumption.

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

2013 ◽  
Vol 22 (10) ◽  
pp. 1340033 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
YIWEI SONG ◽  
JUN LIAO ◽  
JUNFENG GENG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Readout Integrated Circuit ◽  
Chip Area ◽  
Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

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