Low-power stack pseudo domino logic using contention-alleviated precharge keeper

2016 International Conference on Information Technology (InCITe) - The Next Generation IT Summit on the Theme - Internet of Things: Connect your Worlds ◽

10.1109/incite.2016.7857614 ◽

2016 ◽

Author(s):

Deepika Bansal ◽

B. P. Singh ◽

Ajay Kumar

Keyword(s):

Low Power ◽

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A Novel Low Power Dynamic Barrel Shifter using Footed Diode Domino Logic

2017 International Conference on Current Trends in Computer, Electrical, Electronics and Communication (CTCEEC) ◽

10.1109/ctceec.2017.8455194 ◽

2017 ◽

Author(s):

M. RoopaNandini ◽

P. Mor

Keyword(s):

Low Power ◽

Domino Logic ◽

Power Dynamic ◽

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A Novel Low-Power Domino Logic Technique Providing Static Output in Evaluation Phase for High Frequency Changing Inputs

Advances in Intelligent Systems and Computing - Intelligent Computing, Communication and Devices ◽

10.1007/978-81-322-2012-1_47 ◽

2014 ◽

pp. 455-463

Author(s):

Sumit Sharma ◽

Kamal Kant Kashyap

Keyword(s):

Low Power ◽

High Frequency ◽

Domino Logic ◽

Evaluation Phase ◽

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A Low-Power Domino Logic Architecture for Memristor-Based Neuromorphic Computing

Proceedings of the International Conference on Neuromorphic Systems - ICONS '19 ◽

10.1145/3354265.3354282 ◽

2019 ◽

Author(s):

Cory Merkel ◽

Animesh Nikam

Keyword(s):

Low Power ◽

Neuromorphic Computing ◽

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Design of Low Power and High Speed VLSI Domino Logic Circuit

2018 4th International Conference on Applied and Theoretical Computing and Communication Technology (iCATccT) ◽

10.1109/icatcct44854.2018.9001989 ◽

2018 ◽

Author(s):

Praveen J ◽

Aishwarya Aishwarya ◽

Jagadish Venkatraman Naik ◽

Kshithija Kshithija ◽

Mahesh Biradar

Keyword(s):

Low Power ◽

Logic Circuit ◽

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A comprehensive operand-aware dynamic clock gating scheme for low-power Domino Logic

2013 IEEE International SOC Conference ◽

10.1109/socc.2013.6749714 ◽

2013 ◽

Author(s):

Salim Farah ◽

Magdy Bayoumi

Keyword(s):

Low Power ◽

Clock Gating ◽

Domino Logic ◽

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Sub-Domino logic: ultra-low power dynamic sub-threshold digital logic

VLSI Design 2001. Fourteenth International Conference on VLSI Design ◽

10.1109/icvd.2001.902662 ◽

2002 ◽

Author(s):

H. Soeleman ◽

K. Roy ◽

B. Paul

Keyword(s):

Low Power ◽

Digital Logic ◽

Domino Logic ◽

Ultra Low Power ◽

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A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2008.917561 ◽

2008 ◽

Vol 16 (5) ◽

pp. 594-598 ◽

Author(s):

Chua-Chin Wang ◽

Chi-Chun Huang ◽

Ching-Li Lee ◽

Tsai-Wen Cheng

Keyword(s):

Low Power ◽

Threshold Voltage ◽

Domino Logic ◽

Dual Threshold Voltage

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Leakage control techniques for designing robust, low power wide-OR domino logic for sub-130nm CMOS technologies

International Symposium on Signals Circuits and Systems Proceedings SCS 2003 (Cat No 03EX720) ISQED-04 ◽

10.1109/isqed.2004.1283709 ◽

2004 ◽

Author(s):

B. Chatterjee ◽

M. Sachdev ◽

R. Krishnamurthy

Keyword(s):

Low Power ◽

Domino Logic ◽

Control Techniques ◽

Leakage Control

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Asymmetric dual-gate multi-fin keeper bias options and optimization for low power and robust FinFET domino logic

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems ◽

10.1109/apccas.2008.4746371 ◽

2008 ◽

Author(s):

Sherif A. Tawfik ◽

Volkan Kursun

Keyword(s):

Low Power ◽

Domino Logic ◽

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Low Power and High Performance Clock Delayed Domino Logic using Saturated Keeper

2006 IEEE International Conference on Acoustics Speed and Signal Processing Proceedings ◽

10.1109/iscas.2006.1693299 ◽

2006 ◽

Author(s):

A. Amirabadi ◽

A. Chehelcheraghi ◽

S.H. Rasouli ◽

A. Seyedi ◽

A. Afzai-Kusha

Keyword(s):

Low Power ◽

High Performance ◽

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