A Novel Low Power Dynamic Barrel Shifter using Footed Diode Domino Logic

2017 International Conference on Current Trends in Computer, Electrical, Electronics and Communication (CTCEEC) ◽

10.1109/ctceec.2017.8455194 ◽

2017 ◽

Author(s):

M. RoopaNandini ◽

P. Mor

Keyword(s):

Low Power ◽

Domino Logic ◽

Power Dynamic ◽

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Sub-Domino logic: ultra-low power dynamic sub-threshold digital logic

VLSI Design 2001. Fourteenth International Conference on VLSI Design ◽

10.1109/icvd.2001.902662 ◽

2002 ◽

Author(s):

H. Soeleman ◽

K. Roy ◽

B. Paul

Keyword(s):

Low Power ◽

Digital Logic ◽

Domino Logic ◽

Ultra Low Power ◽

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Design and simulation of low power dynamic logic circuit using footed diode domino logic

2013 Students Conference on Engineering and Systems (SCES) ◽

10.1109/sces.2013.6547509 ◽

2013 ◽

Author(s):

S. Kumar ◽

S. Singhal ◽

A. K. Pandey ◽

R. K. Nagaria

Keyword(s):

Low Power ◽

Dynamic Logic ◽

Logic Circuit ◽

Domino Logic ◽

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An ultra low-power dynamic translinear cardiac sense amplifier for pacemakers

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. ◽

10.1109/iscas.2003.1206168 ◽

2003 ◽

Author(s):

S.A.P. Haddad ◽

S. Gieltjes ◽

R. Houben ◽

W.A. Serdijn

Keyword(s):

Low Power ◽

Ultra Low Power ◽

Power Dynamic ◽

Sense Amplifier

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High Speed, Low Power Dynamic Comparator with Dynamic Biasing in Pre-amplifier Phase

2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) ◽

10.1109/icsict.2018.8564870 ◽

2018 ◽

Author(s):

Jingchao Lan ◽

Yongzhen Chen ◽

Zhekan Ni ◽

Fan Ye ◽

Junyan Ren

Keyword(s):

Low Power ◽

Dynamic Comparator ◽

Power Dynamic ◽

Dynamic Biasing

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Ultra‐low‐voltage low‐power dynamic comparator with forward body bias scheme for SAR ADC

Electronics Letters ◽

10.1049/el.2018.6340 ◽

2018 ◽

Vol 54 (24) ◽

pp. 1370-1372 ◽

Author(s):

Young‐Ha Hwang ◽

Deog‐Kyoon Jeong

Keyword(s):

Low Power ◽

Low Voltage ◽

Sar Adc ◽

Dynamic Comparator ◽

Power Dynamic ◽

Forward Body Bias ◽

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Low Power Dynamic Comparator Design for High Speed ADC Application

2018 International Conference on Current Trends towards Converging Technologies (ICCTCT) ◽

10.1109/icctct.2018.8550868 ◽

2018 ◽

Author(s):

K. Arunkumar ◽

R. Ramesh ◽

R. Geethalakshmi ◽

T. Archana

Keyword(s):

Low Power ◽

Dynamic Comparator ◽

Power Dynamic ◽

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Design optimization of Reversible Logic Universal Barrel Shifter for Low Power applications

International Journal of Computer Applications ◽

10.5120/5057-7379 ◽

2012 ◽

Vol 40 (15) ◽

pp. 26-34 ◽

Author(s):

Ravish AradhyaHV ◽

Lakshmesha J ◽

Muralidhara K N

Keyword(s):

Low Power ◽

Design Optimization ◽

Reversible Logic ◽

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LOW-POWER DYNAMIC COMPARATOR WITH HIGH PRECISION FOR SAR ADC

Turkish Journal of Engineering ◽

10.31127/tuje.625475 ◽

2020 ◽

Author(s):

Ersin Alaybeyoğlu

Keyword(s):

Low Power ◽

High Precision ◽

Sar Adc ◽

Dynamic Comparator ◽

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Low-Power Dynamic Memory Word Line Decoding for Static Random Access Memories

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2008.2005813 ◽

2008 ◽

Vol 43 (11) ◽

pp. 2524-2532 ◽

Author(s):

Giby Samson ◽

Nagaraj Ananthapadmanabhan ◽

Sayeed A. Badrudduza ◽

Lawrence T. Clark

Keyword(s):

Low Power ◽

Random Access ◽

Dynamic Memory ◽

Power Dynamic ◽

Static Random Access Memories ◽

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A Novel Low-Power Domino Logic Technique Providing Static Output in Evaluation Phase for High Frequency Changing Inputs

Advances in Intelligent Systems and Computing - Intelligent Computing, Communication and Devices ◽

10.1007/978-81-322-2012-1_47 ◽

2014 ◽

pp. 455-463

Author(s):

Sumit Sharma ◽

Kamal Kant Kashyap

Keyword(s):

Low Power ◽

High Frequency ◽

Domino Logic ◽

Evaluation Phase ◽

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