Loop dissevering: a technique for temporally partitioning loops in dynamically reconfigurable computing platforms

2004 ◽  
Author(s):  
J.M.P. Cardoso
Keyword(s):  
Reconfigurable Computing ◽  
Dynamically Reconfigurable ◽  
Computing Platforms

scholarly journals FPGA-Based On-Board Hyperspectral Imaging Compression: Benchmarking Performance and Energy Efficiency against GPU Implementations

2020 ◽  
Vol 12 (22) ◽  
pp. 3741 ◽  
Author(s):  
Julián Caba ◽  
María Díaz ◽  
Jesús Barba ◽  
Raúl Guerra ◽  
Jose A. de la Torre and Sebastián López
Keyword(s):  
Reconfigurable Computing ◽  
Power Efficiency ◽  
Real Life ◽  
Hyperspectral Data ◽  
Actual Behavior ◽  
Power Budget ◽  
Image Block ◽  
Power Efficient ◽  
Time Requirements ◽  
Computing Platforms

Remote-sensing platforms, such as Unmanned Aerial Vehicles, are characterized by limited power budget and low-bandwidth downlinks. Therefore, handling hyperspectral data in this context can jeopardize the operational time of the system. FPGAs have been traditionally regarded as the most power-efficient computing platforms. However, there is little experimental evidence to support this claim, which is especially critical since the actual behavior of the solutions based on reconfigurable technology is highly dependent on the type of application. In this work, a highly optimized implementation of an FPGA accelerator of the novel HyperLCA algorithm has been developed and thoughtfully analyzed in terms of performance and power efficiency. In this regard, a modification of the aforementioned lossy compression solution has also been proposed to be efficiently executed into FPGA devices using fixed-point arithmetic. Single and multi-core versions of the reconfigurable computing platforms are compared with three GPU-based implementations of the algorithm on as many NVIDIA computing boards: Jetson Nano, Jetson TX2 and Jetson Xavier NX. Results show that the single-core version of our FPGA-based solution fulfils the real-time requirements of a real-life hyperspectral application using a mid-range Xilinx Zynq-7000 SoC chip (XC7Z020-CLG484). Performance levels of the custom hardware accelerator are above the figures obtained by the Jetson Nano and TX2 boards, and power efficiency is higher for smaller sizes of the image block to be processed. To close the performance gap between our proposal and the Jetson Xavier NX, a multi-core version is proposed. The results demonstrate that a solution based on the use of various instances of the FPGA hardware compressor core achieves similar levels of performance than the state-of-the-art GPU, with better efficiency in terms of processed frames by watt.

A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing

2010 ◽  
Vol 45 (8) ◽  
pp. 1615-1626 ◽  
Author(s):  
Davide Rossi ◽  
Fabio Campi ◽  
Simone Spolzino ◽  
Stefano Pucillo ◽  
Roberto Guerrieri
Keyword(s):  
Digital Signal Processor ◽  
Reconfigurable Computing ◽  
Digital Signal ◽  
Dynamically Reconfigurable ◽  
Signal Processor

A Novel Scheduling Algorithm for Dynamically Reconfigurable Computing Systems

2008 ◽  
Author(s):  
Bouraoui Ouni ◽  
Ayadi Ramzi ◽  
Abdellatif Mtibaa ◽  
Mohamed Abid
Keyword(s):  
Reconfigurable Computing ◽  
Scheduling Algorithm ◽  
Computing Systems ◽  
Dynamically Reconfigurable

Dynamically Reconfigurable Hardware for Evolving Bio-Inspired Architectures

2010 ◽  
pp. 1-22 ◽  
Author(s):  
Andres Upegui
Keyword(s):  
Reconfigurable Computing ◽  
High Performance ◽  
Environmental Changes ◽  
Boolean Networks ◽  
Research Field ◽  
Evolvable Hardware ◽  
Neuron Models ◽  
Random Boolean Networks ◽  
Dynamically Reconfigurable ◽  
Spiking Neuron Models

During the last few years, reconfigurable computing devices have experienced an impressive development in their resource availability, speed, and configurability. Currently, commercial FPGAs offer the possibility of self-reconfiguring by partially modifying their configuration bit-string, providing high architectural flexibility, while guaranteeing high performance. On the other hand, we have bio-inspired hardware, a large research field taking inspiration from living beings in order to design hardware systems, which includes diverse approaches like evolvable hardware, neural hardware, and fuzzy hardware. Living beings are well known for their high adaptability to environmental changes, featuring very flexible adaptations at several levels. Bio-inspired hardware systems require such flexibility to be provided by the hardware platform on which the system is implemented. Even though some commercial FPGAs provide enhanced reconfigurability features such as partial and dynamic reconfiguration, their utilization is still in the early stages and they are not well supported by FPGA vendors, thus making their inclusion difficult in existing bio-inspired systems. This chapter presents a set of methodologies and architectures for exploiting the reconfigurability advantages of current commercial FPGAs in the design of bio-inspired hardware systems. Among the presented architectures are neural networks, spiking neuron models, fuzzy systems, cellular automata and Random Boolean Networks.

Introduction to Reconfigurable Computing Platforms

2002 ◽  
pp. 607-609
Author(s):  
Giovanni De Micheli ◽  
Rolf Ernst ◽  
Wayne Wolf
Keyword(s):  
Reconfigurable Computing ◽  
Computing Platforms
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