A low-voltage CMOS op amp with a rail-to-rail constant-gm input stage and a class ab rail-to-rail output stage

Author(s):  
J.H. Botma ◽  
R.F. Wassenaar ◽  
R.J. Wiegerink
1994 ◽  
Vol 6 (2) ◽  
pp. 121-133 ◽  
Author(s):  
Jacob H. Botma ◽  
Remco J. Wiegerink ◽  
Sander L. J. Gierkink ◽  
Roelof F. Wassenaar

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.


Author(s):  
J. Ramirez-Angulo ◽  
M.-S. Sawant ◽  
S. Thoutam ◽  
A.J. Lopez-Martin ◽  
R.G. Carvajal

2013 ◽  
Vol 380-384 ◽  
pp. 3304-3307
Author(s):  
Yang Guang ◽  
Bin Yu ◽  
Huang Hai

In this paper, an operational amplifier with low-power consumption has been designed. Using the complementary differential pair for the input stage and the class AB structure for the output stage, the common-mode input range and output swing of the proposed circuit could achieved rail-to-rail. Based on TSMC 0.18μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that the proposed op-amp has more than 100dB open loop gain, meanwhile the static power consumption is less than 300μw. The circuit's phase margin is 68 degrees, CMRR is 135dB and power supply rejection ratio is 63dB.


Sign in / Sign up

Export Citation Format

Share Document