A pseudo-BiCMOS high gain-bandwidth low noise operational amplifier using a Darlington input stage

Author(s):  
W.T. Holman ◽  
J.A. Connelly
2013 ◽  
Vol 389 ◽  
pp. 573-578
Author(s):  
Ming Xin Song ◽  
Yue Li ◽  
Meng Meng Xu

A high-gain folded cascode operational amplifier is presented. Structure of folded cascode operational amplifier and manual calculations are discussed in detail. Folded cascode structure for the input stage is adopted. Folded cascode structure can increase the gain and the value of PSRR. Folded cascode structure can also allow self-compensation at the output. The operational amplifier is designed in 0.35μm CMOS process with 5V power supply. The operational amplifier has high-gain and work steadily. The results of SPICE simulations are shown that the operational amplifier achieved dc gain of 110dB with unity-gain bandwidth of 74.3MHz and phase margin of 54.4 degree.


2014 ◽  
Vol 2 (4) ◽  
pp. 152-160
Author(s):  
Milad Piry ◽  
Mona Khajani Moaf ◽  
Parviz Amiri

2020 ◽  
Vol 10 (23) ◽  
pp. 8376
Author(s):  
Hyungseup Kim ◽  
Yongsu Kwon ◽  
Donggeun You ◽  
Hyun-Woong Choi ◽  
Seong Hyun Kim ◽  
...  

This paper presents a low-noise chopper operational amplifier using a lateral PNP input stage with bipolar junction transistor (BJT) current mirror base current cancellation. The BJT has a lower noise characteristic than the metal–oxide–semiconductor (MOS) transistor, where low-noise characteristics can be achieved by implanting the BJT to the input stage of the amplifier; however, the base current of the BJT input stage causes low input impedance of the amplifier. The BJT current mirror base current cancellation technique is implemented to enhance the input impedance of the BJT input stage by canceling the base current. BJT current mirror base current cancellation is implemented with a simple scheme using NPN transistors with deep n-well in a generic complementary metal–oxide–semiconductor (CMOS) process. For further noise reduction with the BJT input stage, a chopper amplifier scheme is adopted to reduce low-frequency components such as 1/f noise terms in the low-frequency range. The prototype chip is fabricated in a 0.18-μm CMOS process. The active area of the prototype amplifier is 0.213 mm2. The measured input-referred noise is 5.43 nV/√Hz. The measured input base current of the amplifier with base current cancellation is 67.971 nA. The total amplifier current consumption is 278.3 μA, with a power supply of 3.3 V.


Author(s):  
Anne Rouvie ◽  
Daniele Carpentier ◽  
Jean Decobert ◽  
Nadine Lagay ◽  
Frederic Pommereau ◽  
...  

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