A Bulk-Driven Quasi-Floating Gate Regulated Cascode Current Mirror and Its Application in Squarer Circuit

A regulated cascode current mirror (RGC) and its improved version with bulk driven quasi floating gate technique (BD-QFG) are presented in this paper. The proposed BD-QFG RGC current mirror (CM) is compared with the conventional (GD) RGC CM to show the performance improvement. The conventional and unconventional CM are implemented in Candace Virtuoso using 90 nm CMOS technology. For input current (Iin) varied from 0 to 200 μA and for 0.8 V supply voltage, the simulation results present that the proposed BD-QFG RGC CM has less variation in current transfer error (0.2%) as compared to the GD RGC CM (12%). The output voltage requirement for 200 µA input current is respectively 0.7 V and 0.17 V for the GD RGC CM and the BD-QFG RGC CM. The power consumption of the proposed circuit is 22.71 μW which is 0.15 μW higher than the GD RGC (22.56 μW). The total harmonic distortion (THD) of the proposed circuit is 0.4% which is 1.1% less than the conventional circuit (1.5%). All these improvements in the proposed BD-QFG RGC CM are attained at a cost of 0.05 GHz reduction in frequency (2.31 GHz). The minimum supply voltage of BD-QFG RGC CM and GD RGC CM is 0.4 V and

Design of Low Voltage Quasi-floating Self Cascode Current Mirror

In this paper, a modified structure of self-cascode structure is proposed. In the proposed structure, the MOSFET working in saturation mode is replaced by a Quasi-floating gate MOSFET by which the threshold voltage can be scaled, resulting in an increase in the drain-to-source voltage of other MOSFET operating in the linear region. The increased drain-to-source voltage results in a change in the operating region, which here is from linear to saturation regime. To exploit the performance of the proposed structure, the design of the current mirror circuit is shown in this paper. The proposed architecture when compared with its conventional design showed improvement in performance without affecting the other parameters. The complete design is done using MOSFET models of 180nm technology using Spice at supply dual supply of 0.5V.