In-Pixel CTIA & Readout Circuitry for an Active CMOS Image Sensor

This work aims to design and simulate an in-pixel Capacitive Transimpedance Amplifier (CTIA) and peripheral circuitry that ensures pixel reading. Each pixel circuit is composed of four transistors using 90nm CMOS technology with a supply voltage of 1.8 V and is part of an array of pixels that make up a CMOS image sensor with peripheral circuitry. Pixel output is sent to a delta difference sampling (DDS) circuit to filter reset voltages. The Gain Margin achieved for the in-pixel CTIA is 44dB and 91dB for the Phase Margin. We also present measured pixel parameters and give a comparison with prior work. The timing and readout circuitry is also described.

A 2D model for the study of equilibrium glide paths of UiS Subsea Freight-Glider

A planar mathematical model for the analysis of equilibrium glide paths of the UiS subsea freight-glider (USFG) is presented. The model is developed using Simscape Multibody in MATLAB/Simulink to study the ever-changing dynamics of the glider. Motion along the heave and pitch direction is regulated by two separate PID controllers. Controllers are tuned for the optimal bandwidth and phase margin to provide the system with ideal gains which satisfy the system requirements. A wide-ranging sensitivity investigation is carried out on the USFG by changing the two key variables, pump flow rate and ballast fraction. The results reflect the advantages of using higher flow capacity and ballast fraction, which should be preferred according to the application, provided if there are no space and weight restrictions. Finally, different glide paths were simulated to observe that, controller gains obtained from the linear model can be improved to acquire better performance in terms of robustness and stability of the system.

A High Bandwidth-Power Efficiency, Low THD2,3 Driver Amplifier with Dual-Loop Active Frequency Compensation for High-Speed Applications

This paper presents a driver amplifier with high bandwidth-power efficiency, high capacitor-driving capacity, and low total harmonic distortion (THD). One complementary differential pair composed of self-cascode transistors is incorporated to obtain a full input voltage swing. Flipped voltage follower (FVF) buffers are applied as second stage to drive the last class-AB output stage. Moreover, a dual-loop active-feedback frequency compensation (DLAFC) is presented, which can stabilize the proposed multistage amplifier and keep the dominant pole on high frequency to obtain high-frequency total harmonic distortion (THD) suppression. To achieve a low-frequency phase margin protection (PMP), one left half-plane (LHP) zero is introduced to compensate for the nondominant pole caused by the load capacitor. Meanwhile, two high-frequency LHP zeros are injected to achieve high-frequency phase margin boosting (PMB) and reduce the amplifier’s settling time and integration area. This proposed amplifier is implemented in a standard DBH 0.18 μm 5 V CMOS process, and it achieves over 115-dB DC gain, 150–300 MHz GBW under 0–100 p load capacitors, ultra-high THD2,3 suppression ranges from 100 kHz to 10 MHz under 1–2 V output swing, and over 250 V/μs average slew rate, by only dissipating 12.5 mW at 5 V power supply.

A High Gain, High BW OP AMP with Frequency Compensation Techniques at 65 nm Technology

OP-AMPs finds applications in different domains of electronics engineering including communications. There has been several OP-AMP configurations realized in the last decades for different target applications. But with the evolution of communication standards, to meet the demand for high data rate over the years, requirement for a high frequency and high BW OP-AMP is gaining attention. This makes the design challenge much higher. This paper presents a two-stage CMOS amplifier which uses frequency compensation method to facilitate higher BW. Different parameters like Gain, Gain band width product (GBWP), Phase Margin and Total Power dissipation are considered in this design. A step-by-step procedure for an efficient amplifier design is followed using frequency compensation. We have achieved a gain-bandwidth product (GBWP) of 110 MHz that is capable of driving large capacitive loads. It also achieves 77.7 dB gain with a phase margin of 60o.

Design of FOPID controller for higher order continuous interval system using improved approximation ensuring stability

This contribution deals with the design of a fractional-order proportional-integral-derivative (FOPID) controller through reduce-order modeling for continuous interval systems. First, a higher order interval plant (HOIP) is considered. The reduced-order interval plant (ROIP) for considered HOIP is derived by multipoint Padé approximation integrated with Routh table. Then, FOPID controller is designed for ROIP to satisfy the phase margin and gain cross over frequency. Thus obtained FOPID controller is implemented on HOIP also to validate the performance of designed FOPID on HOIP. A single-input-single-output (SISO) test system is taken up to elaborate the entire process of controller design. The outcomes affirm the validity of the designed FOPID controller. The designed FOPID controller produced stable results retaining the phase margin and gain cross-over frequency when implemented on HOIP. The results further proved that FOPID controller is working efficiently for ROIP and HOIP.

Analytical Expressions for Voltage Controller Coefficients to Attain Desired Values of Total Harmonic Distortion and DC Link Voltage Undershoot in Power Factor Correction Rectifiers

The paper reveals analytical expressions linking the coefficients of PI controller, typically employed as voltage loop compensator of power factor correction rectifiers (PFCR), with two major performance merits (namely, total harmonic distortion (THD) of grid-side current and DC-link voltage deviation upon sudden load increase) and DC link capacitance to rated power ratio. The proposed methodology allows to concretize the commonly used "8–10Hz crossover frequency, 45 degree–70 degree phase margin" rule-of-thumb, typically utilized in application notes of commercial PFC controllers. Relations between voltage loop gain crossover frequency and phase margin as well as settling time of DC-link voltage response to a step load increase to the above mentioned performance merits are also derived in the paper. Provided design guidelines allow to precisely achieve desired values of the two mentioned performance merits and indicate the feasible range of possible DC link capacitance values. Proposed quantitative design guidelines are well-supported by experiments.

Analytical Expressions for Voltage Controller Coefficients to Attain Desired Values of Total Harmonic Distortion and DC Link Voltage Undershoot in Power Factor Correction Rectifiers

The paper reveals analytical expressions linking the coefficients of PI controller, typically employed as voltage loop compensator of power factor correction rectifiers (PFCR), with two major performance merits (namely, total harmonic distortion (THD) of grid-side current and DC-link voltage deviation upon sudden load increase) and DC link capacitance to rated power ratio. The proposed methodology allows to concretize the commonly used "8–10Hz crossover frequency, 45 degree–70 degree phase margin" rule-of-thumb, typically utilized in application notes of commercial PFC controllers. Relations between voltage loop gain crossover frequency and phase margin as well as settling time of DC-link voltage response to a step load increase to the above mentioned performance merits are also derived in the paper. Provided design guidelines allow to precisely achieve desired values of the two mentioned performance merits and indicate the feasible range of possible DC link capacitance values. Proposed quantitative design guidelines are well-supported by experiments.