Mixed-mode parameter analysis of fully differential circuits

Author(s):  
T. Rahkonen ◽  
J. Kortekangas
2013 ◽  
Vol 1 (2) ◽  
pp. 103
Author(s):  
Enrique Mario Spinelli ◽  
Gemma Hornero ◽  
Oscar Casas ◽  
Marcelo Haberman

2012 ◽  
Vol 1 (2) ◽  
pp. 103 ◽  
Author(s):  
Enrique Mario Spinelli ◽  
Gemma Hornero ◽  
Oscar Casas ◽  
Marcelo Haberman

2012 ◽  
Vol 10 (4) ◽  
pp. 1889-1892 ◽  
Author(s):  
Enrique Spinelli ◽  
Marcelo Haberman

2016 ◽  
Vol 25 (09) ◽  
pp. 1650106 ◽  
Author(s):  
Chen-Nong Lee

None of the previously reported mixed-mode universal filters can achieve the following important advantage: no need of component matching conditions. This paper presents a new mixed-mode (including voltage, current, transadmittance, and transimpedance modes) universal biquadratic filter with no need of matching conditions (including no need of component matching and no need of input matching conditions). The proposed filter structure with nine outputs employs two plus-type fully differential current conveyors (P-type FDCCIIs), two grounded capacitors, four grounded resistors and one floating/grounded resistor, which can realize voltage, current, transadmittance, and transimpedance modes universal filtering responses (lowpass, highpass, bandpass, notch, and allpass) from the same topology without matching conditions. Moreover, the proposed circuit still offers many important advantages: the employment of two grounded capacitors, the simultaneous realizations of a lot of filtering functions, using only grounded resistors as the control factors of all filter parameters and gains, having controllable gains in current and transimpedance modes without disturbing filter parameters [Formula: see text], [Formula: see text]/Q, and Q, cascadably connecting the former voltage-mode (VM) stage and the latter current-mode (CM) stage, no capacitors bringing extra poles degrading high-frequency performance, and low active and passive sensitivity performances. H-spice simulations with TSMC 0.18[Formula: see text][Formula: see text]m 1[Formula: see text]P6M CMOS process technology validate theoretical predictions.


2012 ◽  
Vol 2012 ◽  
pp. 1-17 ◽  
Author(s):  
Wilmar Carvajal ◽  
Wilhelmus Van Noije

This paper presents a 6 bit, 11 MS/s time-interleaved pipeline A/D converter design. The specification process, from block level to elementary circuits, is gradually covered to draw a design methodology. Both power consumption and mismatch between the parallel chain elements are intended to be reduced by using some techniques such as double and bottom-plate sampling, fully differential circuits, RSD digital correction, and geometric programming (GP) optimization of the elementary analog circuits (OTAs and comparators) design. Prelayout simulations of the complete ADC are presented to characterize the designed converter, which consumes 12 mW while sampling a 500 kHz input signal. Moreover, the block inside the ADC with the most stringent requirements in power, speed, and precision was sent to fabrication in a CMOS 0.35 μm AMS technology, and some postlayout results are shown.


2000 ◽  
Vol 8 (2) ◽  
pp. 113-128 ◽  
Author(s):  
M. Lubaszewski ◽  
S. Mir ◽  
V. Kolarik ◽  
C. Nielsen ◽  
B. Courtois

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