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Improve accuracy of delay element by filtering false path for low power desychronized circuits
2011 IEEE International Symposium of Circuits and Systems (ISCAS)
◽
10.1109/iscas.2011.5937698
◽
2011
◽
Author(s):
Jun Xu
◽
Xiangku Li
Keyword(s):
Low Power
◽
Delay Element
◽
Improve Accuracy
◽
False Path
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References
Tunable Delay Element for Low Power VLSI Circuit Design
TENCON 2006 - 2006 IEEE Region 10 Conference
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10.1109/tencon.2006.344092
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Cited By ~ 8
Author(s):
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◽
Chih-Wei Chao
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Sung-Min Lin
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◽
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A low power thyristor-based CMOS programmable delay element
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)
◽
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◽
2004
◽
Cited By ~ 13
Author(s):
J. Zhang
◽
S.R. Cooper
◽
A.R. LaPietra
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M.W. Mattern
◽
R.M. Guidash
◽
...
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A Low Power Tunable Delay Element Suitable for Asynchronous Delays of Burst Information
IEEE Journal of Solid-State Circuits
◽
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2008
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pp. 1227-1234
◽
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Author(s):
Bob Schell
◽
Yannis Tsividis
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◽
Delay Element
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A novel low-power and high-performance dual-loop DLL with linear delay element
2008 51st Midwest Symposium on Circuits and Systems
◽
10.1109/mwscas.2008.4616911
◽
2008
◽
Cited By ~ 3
Author(s):
M. Gharib
◽
A. Abrishamifar
Keyword(s):
Low Power
◽
High Performance
◽
Delay Element
◽
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A Monotonic Low Power Thyristor-Based CMOS Delay Element
2007 International Conference on Microwave and Millimeter Wave Technology
◽
10.1109/icmmt.2007.381428
◽
2007
◽
Cited By ~ 2
Author(s):
Peng Chu
◽
Yanlong Zhang
◽
Zhiping Wen
◽
Lixin Yu
Keyword(s):
Low Power
◽
Delay Element
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Low power time-domain rail-to-rail comparator with a new delay element for ADC applications
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◽
10.1016/j.vlsi.2020.11.007
◽
2021
◽
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◽
pp. 89-95
Author(s):
Roohollah Sanati
◽
Farzan Khatib
◽
Mohammad Javadian Sarraf
◽
Reihaneh Kardehi Moghaddam
Keyword(s):
Low Power
◽
Time Domain
◽
Delay Element
◽
Rail To Rail
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A power efficient digitally programmable delay element for low power VLSI applications
10.1109/asqed.2009.5206292
◽
2009
◽
Cited By ~ 7
Author(s):
Sekedi Bomeh Kobenge
◽
Huazhong Yang
Keyword(s):
Low Power
◽
Delay Element
◽
Power Efficient
◽
Digitally Programmable
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A new design technique for low power dynamic feedthrough logic with delay element
2015 Global Conference on Communication Technologies (GCCT)
◽
10.1109/gcct.2015.7342651
◽
2015
◽
Author(s):
Arjun Dev
◽
R. K. Sharma
◽
Mayur Varshney
Keyword(s):
Low Power
◽
Design Technique
◽
Delay Element
◽
Power Dynamic
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Temporal sequential logic hardening by design with a low power delay element
2011 12th European Conference on Radiation and Its Effects on Components and Systems
◽
10.1109/radecs.2011.6131300
◽
2011
◽
Cited By ~ 5
Author(s):
Sandeep Shambhulingaiah
◽
Lawrence T. Clark
◽
Thomas J. Mozdzen
◽
Nathan D. Hindman
◽
Srivatsan Chella
◽
...
Keyword(s):
Low Power
◽
Delay Element
◽
Sequential Logic
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A low-voltage, low-power CMOS delay element
IEEE Journal of Solid-State Circuits
◽
10.1109/4.508210
◽
1996
◽
Vol 31
(7)
◽
pp. 966-971
◽
Cited By ~ 75
Author(s):
Gyudong Kim
◽
Min-Kyu Kim
◽
Byoung-Soo Chang
◽
Wonchan Kim
Keyword(s):
Low Power
◽
Low Voltage
◽
Delay Element
◽
Low Power Cmos
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