A 57.2-Gb/s PAM4 Driver for a Segmented Silicon-Photonics Mach-Zehnder Modulator with Extinction Ratio >9-dB in 45-nm RF-SOI CMOS Technology

2021 ◽  
Author(s):  
Qiang Fu ◽  
Min Tan ◽  
Dezhi Xing ◽  
Sizhu Shao ◽  
Zhipeng Hu ◽  
...  
Keyword(s):  
Silicon Photonics ◽  
Extinction Ratio ◽  
Cmos Technology ◽  
Mach Zehnder Modulator ◽  
Soi Cmos

A 44Gbps High Extinction Ratio Silicon Mach-Zehnder Modulator with a 3D-Integrated 28nm FD-SOI CMOS Driver

2017 ◽  
Author(s):  
Zheng Yong ◽  
Stefan Shopov ◽  
Jared C. Mikkelsen ◽  
Robert Mallard ◽  
Jason C.C. Mak ◽  
...  
Keyword(s):  
Extinction Ratio ◽  
High Extinction Ratio ◽  
Mach Zehnder Modulator ◽  
Soi Cmos

Introduction of a Novel Sample Preparation Technique for the Failure Analysis of Silicon Integrated Photonics Modules

2019 ◽  
Author(s):  
Pradip Sairam Pichumani ◽  
Fauzia Khatkhatay
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Silicon Photonics ◽  
Cmos Technology ◽  
Single Step ◽  
Oxide Semiconductor ◽  
Disruptive Technology ◽  
Preparation Technique ◽  
Test Vehicle ◽  
Sample Preparation Technique

Abstract Silicon photonics is a disruptive technology that aims for monolithic integration of photonic devices onto the complementary metal-oxide-semiconductor (CMOS) technology platform to enable low-cost high-volume manufacturing. Since the technology is still in the research and development phase, failure analysis plays an important role in determining the root cause of failures seen in test vehicle silicon photonics modules. The fragile nature of the test vehicle modules warrants the development of new sample preparation methods to facilitate subsequent non-destructive and destructive analysis methods. This work provides an example of a single step sample preparation technique that will reduce the turnaround time while simultaneously increasing the scope of analysis techniques.

scholarly journals Performance analysis of carrier depletion silicon PIN phase shifter

2020 ◽  
Vol 0 (0) ◽  
Author(s):  
Jesuwanth Sugesh Ramesh Gabriel ◽  
Sivasubramanian Arunagiri
Keyword(s):  
Performance Analysis ◽  
Bit Error Rate ◽  
Error Rate ◽  
Phase Shifter ◽  
Extinction Ratio ◽  
Fibre Length ◽  
Data Rate ◽  
Operating Voltage ◽  
Data Centre ◽  
Mach Zehnder Modulator

AbstractIn this paper, we report the performance of a carrier depletion Silicon PIN phase shifter with over layer of 130 nm. It is observed that an optimum intrinsic gap of 250 nm for a device length of 5 mm at 2 V, resulted in Extinction Ratio (ER) of 23.41 dB and Bit Error Rate (BER) of 1.00 × 10−7 is obtained for 50 Gbps. The phase shifter is also designed for length 2 mm with an intrinsic gap of 100 nm at an operating voltage <4 V. The study also reveals that the proposed design for Mach-Zehnder modulator operating at a data rate of 100 Gbps for the concentration of P = 7 × 1017 cm−3 and N = 5 × 1017 cm−3 gives better BER and phase performance. The proposed design was also analysed in an intra-data centre communication setup of fibre length 15 km.

A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology

2012 ◽  
Author(s):  
John Bulzacchelli ◽  
Troy Beukema ◽  
Daniel Storaska ◽  
Ping-Hsuan Hsieh ◽  
Sergey Rylov ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Serial Link ◽  
Serial Link Transceiver ◽  
Soi Cmos

scholarly journals Resonant Body Transistors in IBM's 32 nm SOI CMOS Technology

2014 ◽  
Vol 23 (3) ◽  
pp. 636-650 ◽  
Author(s):  
Radhika Marathe ◽  
Bichoy Bahr ◽  
Wentao Wang ◽  
Zohaib Mahmood ◽  
Luca Daniel ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Soi Cmos
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