A Low-power Low-noise Open-loop Configured Signal Folding Neural Recording Amplifier

2018 ◽  
Author(s):  
Gauri Punekar ◽  
Venkateswarlu Gonuguntla ◽  
Palagani Yellappa ◽  
Jun Rim Choi ◽  
Ramesh Vaddi
Keyword(s):  
Low Power ◽  
Neural Recording ◽  
Open Loop ◽  
Low Noise

A Low-Noise Biopotential CMOS Amplifier IC Using Low-Power Two-Stage OTA for Neural Recording Applications

2018 ◽  
Vol 27 (05) ◽  
pp. 1850068 ◽  
Author(s):  
Hyung Seok Kim ◽  
Hyouk-Kyu Cha
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Cmos Technology ◽  
Neural Recording ◽  
Open Loop ◽  
Low Noise ◽  
Two Stage ◽  
Prosthetic Devices ◽  
Transconductance Amplifier ◽  
Cmos Amplifier

This work presents a low-power biopotential amplifier integrated circuit (IC) for implantable neural recording prosthetic devices which have been implemented using 0.18-[Formula: see text]m CMOS technology. The proposed neural recording amplifier is based on a capacitive-feedback architecture and utilizes a low-power two-stage source-degenerated operational transconductance amplifier (OTA) with a modified current buffer compensation for large open-loop gain, low-noise and wide bandwidth. The designed amplifier achieves a measured gain of 39.2[Formula: see text]dB with a bandwidth between 0.25[Formula: see text]Hz to 28[Formula: see text]kHz, integrated input referred noise of 5.79[Formula: see text][Formula: see text]Vrms and noise efficiency factor of 3.16. The IC consumes 2.4[Formula: see text][Formula: see text]W at 1.2[Formula: see text]V supply and the die area is 0.09[Formula: see text]mm2.

scholarly journals Low-Power Low-Noise Pseudo-Open-Loop Preamplifier for Neural Interfaces

2017 ◽  
Vol 17 (15) ◽  
pp. 4843-4852 ◽  
Author(s):  
Sun-Il Chang ◽  
Sung-Yun Park ◽  
Euisik Yoon
Keyword(s):  
Low Power ◽  
Open Loop ◽  
Low Noise ◽  
Neural Interfaces

scholarly journals Compact Continuous Time Common-Mode Feedback Circuit for Low-Power, Area-Constrained Neural Recording Amplifiers

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 145
Author(s):  
Joon Young Kwak ◽  
Sung-Yun Park
Keyword(s):  
Low Power ◽  
Continuous Time ◽  
Cmos Technology ◽  
Neural Recording ◽  
Low Noise ◽  
Common Mode ◽  
Passive Components ◽  
Fully Differential ◽  
Transconductance Amplifier ◽  
Differential Difference Amplifier

A continuous-time common-mode feedback (CMFB) circuit for low-power, area-constrained neural recording amplifiers is proposed. The proposed CMFB circuit is compact; it can be realized by simply replacing passive components with transistors in a low-noise folded cascode operational transconductance amplifier (FC-OTA) that is one of the most widely adopted OTAs for neural recording amplifiers. The proposed CMFB also consumes no additional power, i.e., no separate CMFB amplifier is required, thus, it fits well to low-power, area-constrained multichannel neural recording amplifiers. The proposed CMFB is analyzed in the implementation of a fully differential AC-coupled neural recording amplifier and compared with that of an identical neural recording amplifier using a conventional differential difference amplifier-based CMFB in 0.18 μm CMOS technology post-layout simulations. The AC-coupled neural recording amplifier with the proposed CMFB occupies ~37% less area and consumes ~11% smaller power, providing 2.67× larger output common mode (CM) range without CM bandwidth sacrifice in the comparison.

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