A Low-Noise Biopotential CMOS Amplifier IC Using Low-Power Two-Stage OTA for Neural Recording Applications

2018 ◽  
Vol 27 (05) ◽  
pp. 1850068 ◽  
Author(s):  
Hyung Seok Kim ◽  
Hyouk-Kyu Cha
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Cmos Technology ◽  
Neural Recording ◽  
Open Loop ◽  
Low Noise ◽  
Two Stage ◽  
Prosthetic Devices ◽  
Transconductance Amplifier ◽  
Cmos Amplifier

This work presents a low-power biopotential amplifier integrated circuit (IC) for implantable neural recording prosthetic devices which have been implemented using 0.18-[Formula: see text]m CMOS technology. The proposed neural recording amplifier is based on a capacitive-feedback architecture and utilizes a low-power two-stage source-degenerated operational transconductance amplifier (OTA) with a modified current buffer compensation for large open-loop gain, low-noise and wide bandwidth. The designed amplifier achieves a measured gain of 39.2[Formula: see text]dB with a bandwidth between 0.25[Formula: see text]Hz to 28[Formula: see text]kHz, integrated input referred noise of 5.79[Formula: see text][Formula: see text]Vrms and noise efficiency factor of 3.16. The IC consumes 2.4[Formula: see text][Formula: see text]W at 1.2[Formula: see text]V supply and the die area is 0.09[Formula: see text]mm2.

scholarly journals Compact Continuous Time Common-Mode Feedback Circuit for Low-Power, Area-Constrained Neural Recording Amplifiers

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 145
Author(s):  
Joon Young Kwak ◽  
Sung-Yun Park
Keyword(s):  
Low Power ◽  
Continuous Time ◽  
Cmos Technology ◽  
Neural Recording ◽  
Low Noise ◽  
Common Mode ◽  
Passive Components ◽  
Fully Differential ◽  
Transconductance Amplifier ◽  
Differential Difference Amplifier

A continuous-time common-mode feedback (CMFB) circuit for low-power, area-constrained neural recording amplifiers is proposed. The proposed CMFB circuit is compact; it can be realized by simply replacing passive components with transistors in a low-noise folded cascode operational transconductance amplifier (FC-OTA) that is one of the most widely adopted OTAs for neural recording amplifiers. The proposed CMFB also consumes no additional power, i.e., no separate CMFB amplifier is required, thus, it fits well to low-power, area-constrained multichannel neural recording amplifiers. The proposed CMFB is analyzed in the implementation of a fully differential AC-coupled neural recording amplifier and compared with that of an identical neural recording amplifier using a conventional differential difference amplifier-based CMFB in 0.18 μm CMOS technology post-layout simulations. The AC-coupled neural recording amplifier with the proposed CMFB occupies ~37% less area and consumes ~11% smaller power, providing 2.67× larger output common mode (CM) range without CM bandwidth sacrifice in the comparison.

A QFGMOS-Based gm-Boosted and Adaptively Biased Two-Stage Amplifier Offering Very High Gain and High Bandwidth

2021 ◽  
pp. 2250056
Author(s):  
Urvashi Bansal ◽  
Abhilasha Bakre ◽  
Prem Kumar ◽  
Devansh Yadav ◽  
Mohit Kumar ◽  
...  
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Open Loop ◽  
Slew Rate ◽  
Two Stage ◽  
Adaptive Biasing ◽  
Unity Gain ◽  
High Bandwidth ◽  
Cmos Amplifier

A low voltage low power two-stage CMOS amplifier with high open-loop gain, high gain bandwidth product (GBW) and enhanced slew rate is presented in this work. The proposed circuit makes use of folded cascode gm-boosting cells in conjunction with a low voltage gain enhanced cascode mirror using quasi-floating gate (QFGMOS) transistors. QFGMOS transistors are also used in input pair and adaptive biasing, which facilitate large dynamic output current in the presented circuit. Consequently, the slew rate is enhanced without much increase in static power dissipation. The unity gain frequency (UGF) and dc gain of the circuit are 29.4[Formula: see text]MHz and 132[Formula: see text]dB, respectively. The amplifier is operated at 0.6[Formula: see text]V dual supply with 89[Formula: see text][Formula: see text]W power consumption and has a nearly symmetrical average slew rate of 51.5[Formula: see text]V/[Formula: see text]s. All simulations including Monte Carlo and corner analysis are carried out using 180-nm CMOS technology for validating the design with help of spice tools.

High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation

2015 ◽  
Vol 24 (04) ◽  
pp. 1550057 ◽  
Author(s):  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Open Loop ◽  
Two Stage ◽  
Miller Compensation ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Folded Cascode

By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of recycling structure, positive feedback and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate and common mode rejection ratio (CMRR). The presented OTA is simulated in 0.18-μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 111 dB open-loop DC gain, 20 MHz UGF and 145 dB CMRR @ 1.2 V supply voltage while the power consumption is 400 μW which makes it suitable for low-voltage applications.

A Low-power Low-noise Open-loop Configured Signal Folding Neural Recording Amplifier

2018 ◽  
Author(s):  
Gauri Punekar ◽  
Venkateswarlu Gonuguntla ◽  
Palagani Yellappa ◽  
Jun Rim Choi ◽  
Ramesh Vaddi
Keyword(s):  
Low Power ◽  
Neural Recording ◽  
Open Loop ◽  
Low Noise

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

High-Count Rate, Low Power and Low Noise Single Electron Readout ASIC in 65nm CMOS Technology

2021 ◽  
Author(s):  
Matthew Al Disi ◽  
Alireza Mohammad Zaki ◽  
Qinwen Fan ◽  
Stoyan Nihtianov
Keyword(s):  
Low Power ◽  
Count Rate ◽  
Cmos Technology ◽  
Low Noise ◽  
Single Electron ◽  
High Count ◽  
High Count Rate
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