A 0.8V 14bit 294kSPS non-binary cyclic ADC in 65nm SOTB CMOS technology

Author(s):  
Eiki Kayama ◽  
Kenta Mori ◽  
Maebou Taichi ◽  
Yuanchi Chen ◽  
Hao San ◽  
...  
Keyword(s):  
Author(s):  
Yuze Niu ◽  
Yacong Zhang ◽  
Zhuo Zhang ◽  
Miaomiao Fan ◽  
Wengao Lu ◽  
...  

This paper presents a two-stage ADC based on pseudo-differential operational transconductance amplifier (OTA), which is designed for the readout circuit of X-ray linear array sensor. This hybrid ADC employs an incremental sigma-delta ADC and a cyclic ADC, achieving a good trade-off between accuracy and conversion speed. The two stages share the same hardware to reduce power consumption and die area. A common-mood feedback module is used to suppress the influence of charge injection, and the effectiveness is demonstrated by detailed theoretical analysis. A test chip of 14-bit ADC is fabricated in 0.35μm CMOS technology. The measured root mean square (RMS) value of DNL is 0.254 LSB, and the maximum value of INL is -0.776/+1.56 LSB. The measured effective number of bits (ENOB) is 13.43 bits.


Author(s):  
Shuichiro Yamada ◽  
Toshiki Ohtsu ◽  
Minami Sasaki ◽  
Hao San ◽  
Tatsuji Matsuura ◽  
...  
Keyword(s):  

1988 ◽  
Vol 49 (C4) ◽  
pp. C4-41-C4-44
Author(s):  
G. J.T. DAVIDS ◽  
P. B. HARTOG ◽  
J. W. SLOTBOOM ◽  
G. STREUTKER ◽  
A. G. van der SIJDE ◽  
...  
Keyword(s):  

1988 ◽  
Vol 49 (C4) ◽  
pp. C4-13-C4-22
Author(s):  
F. NEPPL ◽  
H.-J. PFLEIDERER
Keyword(s):  

1988 ◽  
Vol 49 (C4) ◽  
pp. C4-421-C4-424 ◽  
Author(s):  
A. STRABONI ◽  
M. BERENGUER ◽  
B. VUILLERMOZ ◽  
P. DEBENEST ◽  
A. VERNA ◽  
...  

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