Partial Product Reduction for Parallel Cubing

A multi-stage supply chain network design problem with in-house production and partial product outsourcing

Applied Mathematical Modelling ◽

10.1016/j.apm.2019.01.046 ◽

2019 ◽

Vol 70 ◽

pp. 572-594 ◽

Cited By ~ 6

Author(s):

M.J. Cortinhal ◽

M.J. Lopes ◽

M.T. Melo

Keyword(s):

Supply Chain ◽

Network Design ◽

Design Problem ◽

Network Design Problem ◽

Supply Chain Network Design ◽

Supply Chain Network ◽

Partial Product ◽

Multi Stage ◽

House Production

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Pyrolysis of ethane in the presence of hydrogen sulfide. Rates of formation of ethylene, hydrogen, and methane

Canadian Journal of Chemistry ◽

10.1139/v70-293 ◽

1970 ◽

Vol 48 (11) ◽

pp. 1782-1785 ◽

Cited By ~ 2

Author(s):

P. R. McLean ◽

D. J. McKenney

Keyword(s):

Thermal Decomposition ◽

Hydrogen Sulfide ◽

Quantitative Data ◽

Methane Formation ◽

Partial Product ◽

Complex Mechanism ◽

Product Analysis ◽

Hydrogen Formation

Rates of formation of ethylene, hydrogen, and methane have been measured at 630 °C for the thermal decomposition of ethane at pressures between 100 and 620 Torr, with various pressures (approximately 1 to 100 Torr) of added hydrogen sulfide. The effect of the H2S was to increase the rate of methane formation and to decrease the rate of ethylene and hydrogen formation. Rates of formation of all three of these gases decreased with increasing hydrogen sulfide pressures. The quantitative data obtained and the partial product analysis indicate that a complex mechanism is operative. Possible qualitative explanations for the observations are discussed.

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Ultra-high speed parallel multiplier with new first partial product addition algorithm

ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549) ◽

10.1109/icasic.2001.982633 ◽

2002 ◽

Author(s):

M.M.-O. Lee ◽

Byung Lok Cho

Keyword(s):

High Speed ◽

Partial Product ◽

Parallel Multiplier ◽

Ultra High Speed

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Approximate Multiplier Architectures Through Partial Product Perforation

Proceedings of the 25th edition on Great Lakes Symposium on VLSI - GLSVLSI '15 ◽

10.1145/2742060.2742109 ◽

2015 ◽

Cited By ~ 5

Author(s):

Georgios Zervakis ◽

Kostas Tsoumanis ◽

Sotirios Xydis ◽

Nicholas Axelos ◽

Kiamal Pekmestzi

Keyword(s):

Partial Product

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Design and Implementation of Modified Partial Product Reduction Tree for High Speed Multiplication

International Journal of Reconfigurable and Embedded Systems (IJRES) ◽

10.11591/ijres.v2.i1.pp15-20 ◽

2013 ◽

Vol 2 (1) ◽

pp. 15

Author(s):

Sachin B. Jadhav ◽

Jayamala K. Patil ◽

Ramesh T. Patil

Keyword(s):

Binary Tree ◽

High Speed ◽

Hardware Implementation ◽

Critical Path ◽

Partial Product ◽

Design And Implementation ◽

Multiplication Operation ◽

Multiplication Process ◽

Major Bottleneck ◽

Speed Up

This paper presents the details of hardware implementation of modified partial product reduction tree using 4:2 and 5:2 compressors. Speed of multiplication operation is improved by using higher compressors .In order to improve the speed of the multiplication process within the computational unit; there is a major bottleneck that is needed to be considered that is the partial products reduction network which is used in the multiplication block. For implementation of this stage require addition of large operands that involve long paths for carry propagation. The proposed architecture is based on binary tree constructed using modified 4:2 and 5:2 compressor circuits. Increasing the speed of operation is achieved by using higher modified compressors in critical path. Our objective of work is, to increase the speed of multiplication operation by minimizing the number of combinational gates using higher n:2 compressors. The experimental test of the proposed modified compressor is done using Spartan-3FPGA device (XC3S400 PQ-208). Using tree architectures for the partial products reduction network represent an attractive solution that is frequently applied to speed up the multiplication process. The simulation result shows 4:2 and 5:2 compressor output which is done using Questa Sim 6.4c Mentor Graphics tool.

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On the Multiplication of Decimals

The Mathematical Gazette ◽

10.1017/s0025557200232646 ◽

1908 ◽

Vol 4 (74) ◽

pp. 321-322

Author(s):

A. S. Grant

Keyword(s):

Standard Form ◽

Partial Product ◽

Continued Use

So-called “standard form.”Method I have used with success as regards clearness and accuracy. (I believe this is Mr. Pendlebury’s arrangement.)Ride. Put singles (or units) figure of multiplier under the last figure of multiplicand.Arguments in favour of this second plan :Instead of such a mechanical rule as Mr. Borchardt’s (p. 69, Borchardt’s ,Arithmetical Types and Examples), we get the continued use of the sound and fundamental rule of “putting each first figure of a partial product underneath the figure to which that partial product is due.” And this also corresponds to the method of algebraic multiplication.

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