MULTI-PHASE ROTARY CLOCK SYNCHRONIZATION OF LEVEL-SENSITIVE CIRCUITS

2009 ◽  
Vol 18 (05) ◽  
pp. 899-908 ◽  
Author(s):  
BARIS TASKIN ◽  
IVAN KOURTEV
Keyword(s):  
Phase Synchronization ◽  
Clock Synchronization ◽  
Clock Skew ◽  
Clock Period ◽  
Flip Flop ◽  
Clock Networks ◽  
Significant Performance ◽  
Clock Skew Scheduling ◽  
Time Borrowing ◽  
Multi Phase

Resonant clocking technologies provide clock networks with improved frequency, jitter and power dissipation characteristics, however, often require novel automation routines. Resonant rotary clocking technology, for instance, entails multi-phase and nonzero clock skew operation and supports latch-based design. This paper studies the effects of multi-phase synchronization schemes on the minimum clock period for rotary-clock-synchronized circuits, which necessitate the application of clock skew scheduling and employ level-sensitive registers. In experimentation, single, dual, three- and four-phase clocking schemes generated by rotary clock synchronization are applied to a suite of level-sensitive-transformed ISCAS'89 benchmarks. Average clock period improvements of 30.3%, 24.8%, 17.7% and 12.0%, respectively, are observed on average compared to the flip-flop based, zero clock skew circuits. As the number of clock phases increases, smaller improvements are observed due to lesser overall effectiveness of the complementary effects of clock skew scheduling and time borrowing. It is shown, however, that for some circuits (23% of the benchmarks), multi-phase synchronization leads to significant performance benefits in operating frequency.

scholarly journals Post-CTS Delay Insertion

VLSI Design ◽  
2010 ◽  
Vol 2010 ◽  
pp. 1-9 ◽  
Author(s):  
Jianchao Lu ◽  
Baris Taskin
Keyword(s):  
Programming Model ◽  
Optimization Method ◽  
Clock Skew ◽  
Clock Tree ◽  
Clock Period ◽  
Clock Networks ◽  
Average Improvement ◽  
Clock Tree Synthesis ◽  
Clock Skew Scheduling ◽  
Tree Synthesis

A post-clock-tree-synthesis (post-CTS) optimization method is proposed that suggests delay insertion at the leaves of the clock tree in order to implement a limited version of clock skew scheduling. Delay insertion is limited on each clock tree branch simultaneous with a global monitoring of the total amount of delay insertion. The delay insertion for nonzero clock skew operation is performed only at the clock sinks in order to preserve the structure and the optimizations implemented in the clock tree synthesis stage. The methodology is implemented as a linear programming model amenable to two design objectives: fixing timing violations or optimizing the clock period. Experimental results show that the clock networks of the largest ISCAS'89 circuits can be corrected post-CTS to resolve the timing conflicts in approximately 90% of the circuits with minimal delay insertion (0.159    clock period per clock path on average). It is also shown that the majority of the clock period improvement achievable through unrestricted clock skew scheduling are obtained through very limited insertion (43% average improvement through 10% of max insertion).

STATISTICAL TIMING ANALYSIS OF THE CLOCK PERIOD IMPROVEMENT THROUGH CLOCK SKEW SCHEDULING

2011 ◽  
Vol 20 (05) ◽  
pp. 881-898 ◽  
Author(s):  
SHANNON M. KURTAS ◽  
BARIS TASKIN
Keyword(s):  
Timing Analysis ◽  
Process Variations ◽  
Clock Signal ◽  
Static Timing Analysis ◽  
Clock Skew ◽  
Clock Period ◽  
Static Timing ◽  
Statistical Static Timing Analysis ◽  
Clock Skew Scheduling ◽  
Zero Skew

Statistical static timing analysis (SSTA) methods, which model process variations statistically as probability distribution function rather than deterministically, have been thoroughly performed on traditional zero clock skew circuits. In the traditional zero clock skew circuits, the synchronizing clock signal is designed to arrive in phase with respect to each register. However, designers will often schedule the clock skew to different registers in order to decrease the minimum clock period of the entire circuit. Clock skew scheduling imparts very different timing constraints that are based, in part, on the topology of the circuit. In this paper, SSTA is applied to nonzero clock skew circuits in order to determine the accuracy improvement relative to their zero skew counterparts, and also to assess how the results of skew scheduling might be impacted with more accurate statistical modeling. For 99.7% timing yield (3σ variation), SSTA is observed to improve the accuracy, and therefore increase the timing margin, of nonzero clock skew circuits by up to 2.5×, and on average by 1.3×, the amount seen by zero skew circuits.

A New High Resolution Measurement Technology of D Flip-Flop Output Signals for Measuring Frequency Difference

2013 ◽  
Vol 391 ◽  
pp. 568-571
Author(s):  
Jin Feng Dong ◽  
Wei Yu Zhang ◽  
Hua Liu Liu ◽  
Yong Wei
Keyword(s):  
Absolute Error ◽  
Measurement Technology ◽  
Clock Period ◽  
Flip Flop ◽  
Average Value ◽  
Resolution Measurement ◽  
Measuring Frequency ◽  
The Difference ◽  
Quartz Crystal Resonators ◽  
The Relationship

The output periods of D flip-flop mixer are variable though the periods of two input frequencies are invariable. To measure the output frequency, the conventional method is to calculate the average value of the output periods and the maximum possible absolute error is a clock period. The variation of the output periods has its own pattern of arrangement and it can provide valuable information. Measuring accuracy can be significantly improved by taking into account all the details of output periods changes. A mathematical model that describes the relationship between the input square waves and the output square waves was developed and the difference of two input frequencies can be estimated by the solution of the model. The new method is quite suitable for measuring small frequency increments of quartz crystal resonators.

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