A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits

2014 ◽  
Vol 49 (11) ◽  
pp. 2684-2693 ◽  
Author(s):  
Samantak Gangopadhyay ◽  
Dinesh Somasekhar ◽  
James W. Tschanz ◽  
Arijit Raychowdhury
Author(s):  
Apratim Chatterjee ◽  
Manikandan P

A low dropout regulator is proposed in this paper. The regulator is designed with classic five pack model to decrease the number of devices and make the design compact and also reduce the power consumption. The system is designed and simulated in cadence virtuoso environment under 180nm technology node. Three models of LDO is proposed in this paper, with all having same error amplifier but with small variations. The advantages and disadvantages of each model will be discussed in the paper. The LDOs have linear characteristic over a good input range. It has good transient response to load variation. 


Author(s):  
Venkat Krishnaswamy ◽  
Jeffrey Brooks ◽  
Georgios Konstadinidis ◽  
Curtis McAllister ◽  
Ha Pham ◽  
...  

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