scholarly journals DESIGN OF ONCHIP LOW DROPOUT (LDO) REGULATOR FOR POWER MANAGEMENT APPLICATION

2017 ◽  
Vol 10 (13) ◽  
pp. 1
Author(s):  
Apratim Chatterjee ◽  
Manikandan P
Keyword(s):  
Power Consumption ◽  
Power Management ◽  
Transient Response ◽  
Advantages And Disadvantages ◽  
Error Amplifier ◽  
Linear Characteristic ◽  
Management Application ◽  
Input Range ◽  
Low Dropout Regulator ◽  
Ldo Regulator

A low dropout regulator is proposed in this paper. The regulator is designed with classic five pack model to decrease the number of devices and make the design compact and also reduce the power consumption. The system is designed and simulated in cadence virtuoso environment under 180nm technology node. Three models of LDO is proposed in this paper, with all having same error amplifier but with small variations. The advantages and disadvantages of each model will be discussed in the paper. The LDOs have linear characteristic over a good input range. It has good transient response to load variation. 

An Output-Capacitorless Ultra-Low Power Low-Dropout Regulator

2017 ◽  
Vol 26 (12) ◽  
pp. 1750193 ◽  
Author(s):  
Xin Cheng ◽  
Hongyu Liang ◽  
Longjie Du ◽  
Zhang Zhang ◽  
Maoxiang Yi ◽  
...  
Keyword(s):  
Transient Response ◽  
Cmos Process ◽  
Heavy Load ◽  
Ultra Low Power ◽  
Chip Area ◽  
Error Amplifier ◽  
Light Load ◽  
Gain Stage ◽  
Ldo Regulator ◽  
Overshoot And Undershoot

This paper proposes an output-capacitorless low-dropout (LDO) regulator with ultra-low quiescent power. It applies an adaptive error amplifier to improve the bandwidth and transient response during heavy load, and a second gain stage to improve the stability during light load. Furthermore, an overshoot and undershoot reduction circuit is used to shorten the settling time when output load is changed. The LDO is fabricated in 0.18[Formula: see text][Formula: see text]m CMOS process and occupies a chip area of 0.06[Formula: see text]mm2. The LDO is measured to output a stable voltage at 1.6[Formula: see text]V with a quiescent power of 1.8[Formula: see text][Formula: see text]W. The experimental results also show a good transient response.

scholarly journals A VERY LOW-DROPOUT VOLTAGE REGULATOR IN 0.18-M CMOS TECHNOLOGY FOR POWER MANAGEMENT SYSTEM

2020 ◽  
Vol 82 (6) ◽  
pp. 11-19
Author(s):  
Sohiful Anuar Zainol Murad ◽  
Azizi Harun ◽  
Mohd Nazrin Md Isa ◽  
Saiful Nizam Mohyar ◽  
Jamilah Karim
Keyword(s):  
Power Management ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Voltage Regulator ◽  
Voltage Reference ◽  
Error Amplifier ◽  
Transconductance Amplifier ◽  
Output Capacitor ◽  
Ldo Regulator ◽  
Pmos Transistor

This paper proposes the design of a very low-dropout (LDO) voltage regulator in 0.18-mm CMOS technology. The proposed LDO regulator consists of voltage reference, symmetrical operational transconductance amplifier (OTA), PMOS transistor, resistive feedback network and output capacitor. The NMOS symmetrical OTA is implemented as an error amplifier and a PMOS transistor is employed as a pass device to improve gain and minimize low dropout voltage, respectively. The proposed design is simulated using Spectre simulator in Cadence software to verify its regulator performance. The simulation results show that the proposed LDO is capable to operate from a supply voltage of 1.7-2.0 V with a low dropout voltage of 19.3 mV at a maximum 50 mA load current to regulate output voltage 1.5 V. The active chip is 2.96 mm2 in size. The performance of the proposed LDO is suitable to enhance power management for system on chip (SoC) applications.  

Transient Response Enhancement with Fast Transient Controller for Capacitor-Less LDO Regulator

2014 ◽  
Vol 543-547 ◽  
pp. 800-805 ◽  
Author(s):  
Shang Sheng Chi ◽  
Wei Hu ◽  
Ming Hui Fan ◽  
Yu Sen Xu ◽  
Guo Lin Chen
Keyword(s):  
Transient Response ◽  
Output Voltage ◽  
Input Voltage ◽  
Settling Time ◽  
Voltage Range ◽  
Class Ab ◽  
Response Enhancement ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Ldo Regulator

This paper presents a capacitor-less CMOS low dropout regulator (LDO) with a push-pull class AB amplifier, and a fast transient controller to achieve a better transient response. The undershoot/overshoot voltage and the settling time are effectively reduced. Through the theoretical analysis of the circuit, cadence simulation with SMIC 0.18μm process and under the condition of the input voltage range 1.4~4 V shows the output voltage is 1.2 V, with the fast controller the total quiescent current is 8.2 μA, the undershoot /overshoot voltage is 97 mV/47 mV and the settling time is 0.3 μs as load current suddenly changes from 1 to 100 mA, or vice versa. Compared with this paper without fast transient controller, the undershoot voltage, the overshoot voltage and the settling time are enhanced by 30%, 64% and 80%, respectively.

scholarly journals Stacked Buck Converter: Current Ripple Elimination Effect and Transient Response

Energies ◽  
2020 ◽  
Vol 14 (1) ◽  
pp. 64
Author(s):  
Chien-Chun Huang ◽  
Yu-Chen Liu ◽  
Chia-Ching Lin ◽  
Chih-Yu Ni ◽  
Huang-Jen Chiu
Keyword(s):  
Transient Response ◽  
Dead Time ◽  
Control Method ◽  
Buck Converter ◽  
Modulation Method ◽  
Output Current ◽  
Time Modulation ◽  
Advantages And Disadvantages ◽  
Improvement Method ◽  
Current Ripple

To balance the cost and volume when applying a low output current ripple, the power supply design should be able to eliminate the current ripple under any duty cycle in medium and high switching frequencies, and considerably reduce filter volume to improve power density. A stacked buck converter was eventually selected after reviewing the existing solutions and discussing their advantages and disadvantages. A stacked buck converter is used as a basis to propose the transient response and output current ripple elimination effect, boundary limit control method, and low output ripple dead time modulation method to make individual improvements. The principle, mathematical derivation, small-signal model, and compensator design method of the improvement method are presented in detail. Moreover, simulation results are used to mutually verify the correctness and effectiveness of the improvement method. A stacked buck converter with 330-V input, 50-V output, and 1-kW output power was implemented to verify the effect of the low output current ripple dead time modulation. Experimental results showed that the peak-to-peak value of the output current ripple was reduced from 2.09 A to 559 mA, and the RMS value was reduced from 551 mA to 91 mA, thereby effectively improving the output current ripple.

scholarly journals Efficient Prediction of Network Traffic for Real-Time Applications

2019 ◽  
Vol 2019 ◽  
pp. 1-11 ◽  
Author(s):  
Muhammad Faisal Iqbal ◽  
Muhammad Zahid ◽  
Durdana Habib ◽  
Lizy Kurian John
Keyword(s):  
Power Consumption ◽  
Real Time ◽  
Power Management ◽  
Dynamic Resource Allocation ◽  
Computation Complexity ◽  
Real Time Traffic ◽  
Double Exponential ◽  
Efficient Prediction ◽  
Dynamic Resource ◽  
Double Exponential Smoothing

Accurate real-time traffic prediction is required in many networking applications like dynamic resource allocation and power management. This paper explores a number of predictors and searches for a predictor which has high accuracy and low computation complexity and power consumption. Many predictors from three different classes, including classic time series, artificial neural networks, and wavelet transform-based predictors, are compared. These predictors are evaluated using real network traces. Comparison of accuracy and cost, both in terms of computation complexity and power consumption, is presented. It is observed that a double exponential smoothing predictor provides a reasonable tradeoff between performance and cost overhead.

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