A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50 mV With Fast Settling Time Below 10 ns

2021 ◽  
pp. 1-1
Author(s):  
Young-Ha Hwang ◽  
Jonghyun Oh ◽  
Woo-Seok Choi ◽  
Deog-Kyoon Jeong ◽  
Jun-Eun Park
Keyword(s):  
Settling Time ◽  
Low Dropout Regulator ◽  
Fast Settling

Low-Power Fast-Settling Low-Dropout Regulator Using a Digitally Assisted Voltage Accelerator for DVFS Application

2013 ◽  
Vol 284-287 ◽  
pp. 2526-2530
Author(s):  
Wei Ben Yang ◽  
Chi Hsiung Wang ◽  
Hsiang Hsiung Chang ◽  
Ming Hao Hong ◽  
Jsung Mo Shen
Keyword(s):  
Low Power ◽  
Output Voltage ◽  
Voltage Control ◽  
Control Unit ◽  
Settling Time ◽  
Control Technique ◽  
Dynamic Voltage ◽  
Low Dropout Regulator ◽  
Ldo Regulator ◽  
Fast Settling

This paper presents a low-power fast-settling low-dropout regulator (LDO) using a digitally assisted voltage accelerator. Using the selectable-voltage control technique and digitally assisted voltage accelerator significantly improves the transition response time within output voltage switched. The proposed LDO regulator uses the selectable-voltage control technique to provide two selectable-voltage outputs of 2.5 V and 1.8 V. Using the digitally assisted voltage accelerator when the output voltage is switched reduces the settling time. The simulation results show that the settling time of the proposed LDO regulator is significantly reduced from 4.2 ms to 15.5 μs. Moreover, the selectable-voltage control unit and the digitally assisted voltage accelerator of the proposed LDO regulator consume only 0.54 mW under a load current of 100 mA. Therefore, the proposed LDO regulator is suitable for low-power dynamic voltage and frequency-scaling applications.

HARDWARE DESIGN AND IMPLEMENTATION OF GENETIC ALGORITHM FOR THE CONTROLLER OF A DC TO DC BOOST CONVERTER

2016 ◽  
Vol 78 (5-7) ◽  
Author(s):  
Roderick Yap ◽  
Kevin Lam ◽  
Rovi Bugayong ◽  
Edward Hernandez ◽  
Joey De Guzman
Keyword(s):  
Genetic Algorithm ◽  
Control Method ◽  
Boost Converter ◽  
Settling Time ◽  
Pid Controllers ◽  
Test Results ◽  
Boost Converters ◽  
Kd Values ◽  
Field Programmable ◽  
Fast Settling

Controllers for DC to DC Boost Converters have evolved from simple control method to those that involve the use of fuzzy logic controllers.   In many implementations, Proportional Integral Derivative (PID) controllers are commonly employed.  In this paper, a genetic algorithm for tuning the PID controller of a DC to DC Boost Converter is hardware modelled and implemented on a Field Programmable Gate Array (FPGA) using Verilog as tool for the design entry.  The goal of embedding genetic algorithm into the controller is to search for the best PID parameters that will yield fast settling time of the booster at an output of 6V.  The hardware implementation allows the controller to tune itself by searching for the best Kp, Ki and Kd values that will give the best settling time.  Significantly, this eliminates the need for a separate computer to do the searching routine.   Test results of the circuit implemented yielded promising results.   When compared to previous researches, the genetic algorithm employed yielded good PID parameters that resulted to a settling time as low as less than 60msec.

10-Gb/s Burst-mode Receiver for Fast Settling Time

2009 ◽  
Author(s):  
Daisuke Mashimo ◽  
Jun Sugawa ◽  
Hiroki Ikeda ◽  
Katsuya Minatozaki ◽  
Nobuhiro Matsudaira
Keyword(s):  
Settling Time ◽  
Burst Mode ◽  
Fast Settling

An Improved PLL and its Performance Simulation

2013 ◽  
Vol 427-429 ◽  
pp. 1557-1562
Author(s):  
Wen Jin Zhu ◽  
Yun Feng ◽  
Ming Huang ◽  
Ting Hua Li ◽  
Fu Chun Mao
Keyword(s):  
Noise Suppression ◽  
Settling Time ◽  
Lower Price ◽  
Performance Simulation ◽  
Phase Tracking ◽  
Tracking Ability ◽  
Costas Loop ◽  
Fast Settling

Stability, fast-settling and anti-noise abilities are the three necessary parameters to measure the performance of Phase locked lock (PLL). By using of a LPF with strong noise-suppression ability and replacing multiplier of PD with an adder, an improved PLL is proposed in this paper. Compared with the Costas Loop and Saber's PLL, the proposed PLL has better phase tracking ability, shorter settling time, and stronger anti-noise ability. It is expected that our work will be helpful for developing PLL with lower-price and higher-performance, and then contribute to more applications in communication.

A High Power Supply Rejection and Fast Settling Time Capacitor-Less LDO

2019 ◽  
Vol 34 (1) ◽  
pp. 474-484 ◽  
Author(s):  
Fernando Lavalle-Aviles ◽  
Joselyn Torres ◽  
Edgar Sanchez-Sinencio
Keyword(s):  
High Power ◽  
Power Supply ◽  
Settling Time ◽  
Fast Settling ◽  
Supply Rejection
Sign in / Sign up

Export Citation Format

Share Document