Low-Power Fast-Settling Low-Dropout Regulator Using a Digitally Assisted Voltage Accelerator for DVFS Application

2013 ◽  
Vol 284-287 ◽  
pp. 2526-2530
Author(s):  
Wei Ben Yang ◽  
Chi Hsiung Wang ◽  
Hsiang Hsiung Chang ◽  
Ming Hao Hong ◽  
Jsung Mo Shen
Keyword(s):  
Low Power ◽  
Output Voltage ◽  
Voltage Control ◽  
Control Unit ◽  
Settling Time ◽  
Control Technique ◽  
Dynamic Voltage ◽  
Low Dropout Regulator ◽  
Ldo Regulator ◽  
Fast Settling

This paper presents a low-power fast-settling low-dropout regulator (LDO) using a digitally assisted voltage accelerator. Using the selectable-voltage control technique and digitally assisted voltage accelerator significantly improves the transition response time within output voltage switched. The proposed LDO regulator uses the selectable-voltage control technique to provide two selectable-voltage outputs of 2.5 V and 1.8 V. Using the digitally assisted voltage accelerator when the output voltage is switched reduces the settling time. The simulation results show that the settling time of the proposed LDO regulator is significantly reduced from 4.2 ms to 15.5 μs. Moreover, the selectable-voltage control unit and the digitally assisted voltage accelerator of the proposed LDO regulator consume only 0.54 mW under a load current of 100 mA. Therefore, the proposed LDO regulator is suitable for low-power dynamic voltage and frequency-scaling applications.

Transient Response Enhancement with Fast Transient Controller for Capacitor-Less LDO Regulator

2014 ◽  
Vol 543-547 ◽  
pp. 800-805 ◽  
Author(s):  
Shang Sheng Chi ◽  
Wei Hu ◽  
Ming Hui Fan ◽  
Yu Sen Xu ◽  
Guo Lin Chen
Keyword(s):  
Transient Response ◽  
Output Voltage ◽  
Input Voltage ◽  
Settling Time ◽  
Voltage Range ◽  
Class Ab ◽  
Response Enhancement ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Ldo Regulator

This paper presents a capacitor-less CMOS low dropout regulator (LDO) with a push-pull class AB amplifier, and a fast transient controller to achieve a better transient response. The undershoot/overshoot voltage and the settling time are effectively reduced. Through the theoretical analysis of the circuit, cadence simulation with SMIC 0.18μm process and under the condition of the input voltage range 1.4~4 V shows the output voltage is 1.2 V, with the fast controller the total quiescent current is 8.2 μA, the undershoot /overshoot voltage is 97 mV/47 mV and the settling time is 0.3 μs as load current suddenly changes from 1 to 100 mA, or vice versa. Compared with this paper without fast transient controller, the undershoot voltage, the overshoot voltage and the settling time are enhanced by 30%, 64% and 80%, respectively.

scholarly journals Power Quality Analysis of the Output Voltage of AC Voltage and Frequency Controllers Realized with Various Voltage Control Techniques

2021 ◽  
Vol 11 (2) ◽  
pp. 538
Author(s):  
Naveed Ashraf ◽  
Ghulam Abbas ◽  
Rabeh Abbassi ◽  
Houssem Jerbi
Keyword(s):  
Power Quality ◽  
Output Voltage ◽  
Frequency Control ◽  
Voltage Control ◽  
Voltage Regulation ◽  
Quality Analysis ◽  
Control Technique ◽  
Control Techniques ◽  
Power Quality Analysis ◽  
Selection Of

Single-phase and three-phase AC-AC converters are employed in variable speed drive, induction heating systems, and grid voltage compensation. They are direct frequency and voltage controllers having no intermediate power conversion stage. The frequency controllers govern the output frequency (low or high) in discrete steps as per the requirements. The voltage controllers only regulate the RMS value of the output voltage. The output voltage regulation is achieved on the basis of the various voltage control techniques such as phase-angle, on-off cycle, and pulse-width modulation (PWM) control. The power quality of the output voltage is directly linked with its control techniques. Voltage controllers implemented with a simple control technique have large harmonics in their output voltage. Different control techniques have various harmonics profiles in the spectrum of the output voltage. Traditionally, the evaluation of power quality concerns is based on the simulation platform. The validity of the simulated values depends on the selection of the period of a waveform. Any deficiency in the selection of the period leads to incorrect results. A mathematical analytical approach can tackle this issue. This becomes important to analytically analyze the harmonious contents generated by various switching control algorithms for the output voltage so that these results can be successfully used for power quality analysis and filtering of harmonics components through various harmonics suppression techniques. Therefore, this research is focused on the analytical computation of the harmonics coefficients in the output voltage realized through the various voltage and frequency control techniques. The mathematically computed results are validated with the simulation and experimental results.

A Cap-less Voltage Spike Detection and Correction Circuit for Low Dropout Regulator

2020 ◽  
Vol 29 (16) ◽  
pp. 2020009
Author(s):  
P. Manikandan ◽  
B. Bindu
Keyword(s):  
Steady State ◽  
Output Voltage ◽  
Settling Time ◽  
Spike Detection ◽  
Flipped Voltage Follower ◽  
Output Spike ◽  
Voltage Follower ◽  
Low Dropout Regulator ◽  
Node Voltage ◽  
Voltage Spike

A cap-less voltage spike detection and correction circuit for flipped voltage follower (FVF)-based low dropout regulator (LDO) is proposed in this paper. The transients in the output voltage are controlled by the pull-up currents [Formula: see text] and [Formula: see text] and pull-down currents [Formula: see text] and [Formula: see text]. These currents are dynamic current sources which are activated only during transient period and noise contributed by these current sources at steady state is zero. These currents increase/decrease based on the intermediate FVF node voltage [Formula: see text]. The proposed circuit detects the output voltage via [Formula: see text] and controls the power MOSFET gate and output capacitances by changing the pull-up and pull-down currents whenever the load changes. The proposed circuit consumes small additional bias current in the steady state and achieves less settling time and output spike voltage. This LDO is simulated using 180[Formula: see text]nm technology and the simulation result shows that the LDO has good load transient response with 190[Formula: see text]ns settling time and 170[Formula: see text]mV voltage spike over 1[Formula: see text]mA to 100[Formula: see text]mA load current range.

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