This paper presents the design and implementation of an extended-counting incremental sigma–delta ADC (IDC) with hardware-reuse technique. The proposed ADC architecture is a cascaded configuration of a second-order IDC and a two-stage cyclic ADC. The operation of the ADC consists of the “coarse phase” and the “fine phase”. In the “coarse phase”, the circuit works as an IDC to achieve the most significant bits (MSBs) and produce the residue voltage. Then in the “fine phase”, it is reused and changed to work as a cyclic ADC to quantize the residue voltage and achieve the least significant bits (LSBs). Eventual digital output is achieved by combining the two parts together. The utilization of extended-counting technique significantly reduces the conversion time and increases the conversion rate, and the hardware-reuse technique removes the demand for additional circuit area. The ADC is designed in 0.5[Formula: see text][Formula: see text]m CMOS process, which has a conversion rate of 43.48[Formula: see text]kS/s with oversampling ratio (OSR) of 23 and achieves 84.83[Formula: see text]dB SNDR and 13.799-bit ENOB. It consumes 2.4[Formula: see text]mW with a 5[Formula: see text]V voltage supply, and the FOM is 3.87[Formula: see text]pJ/step.
A 8X Oversampling Ratio, 14bit, 5-MSamples/s Cascade 3-1 Sigma-delta Modulator