Folded cascode CMOS mixer design and optimization in 70 nm technology

Author(s):  
E. Shevchuk ◽  
Kyusun Choi
2010 ◽  
Vol 58 (4) ◽  
pp. 831-840 ◽  
Author(s):  
Pei-Yuan Chiang ◽  
Chao-Wei Su ◽  
Sz-Yun Luo ◽  
Robert Hu ◽  
Christina F Jou
Keyword(s):  

2006 ◽  
Vol 15 (02) ◽  
pp. 183-196 ◽  
Author(s):  
J. J. LIU ◽  
M. A. DO ◽  
X. P. YU ◽  
K. S. YEO ◽  
S. JIANG ◽  
...  

DC offset and high flicker noise are the main problems for the direct conversion CMOS mixer design. A novel even harmonic switching mixer implemented in a standard 0.18 μm CMOS process for applications in 2.45 GHz direct conversion receivers is proposed. The mixer circuit overcomes the problems of DC offset and high flicker noise. It achieves -8.24 dB gain, 5.2 dB DSB noise figure at 100 KHz, 17.25 dBm IIP3 and zero DC power consumption.


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