A passive 2nd-order sigma-delta modulator for low-power analog-to-digital conversion

A re-configurable switched capacitor sigma-delta analog-to-digital conversion architecture1,2 is proposed. The architecture consists of a MASH sigma delta modulator with nth lower-order (first- or second-order) loops cascaded together. Each loop can be powered on or off operating in high or low performance mode, according to application needs. The architecture can be configured to optimize performance and power consumption for specific resolution and applications. The architecture is proven by means of a prototype, implemented as a fourth-order and fabricated in a standard 0.18 um CMOS technology. The outputs of both high performance mode (fourth-order) and medium performance mode (second-order, first loop ON) are measured to demonstrate the configurability. The FFT demonstrates that the noise shaping for the fourth-order modulator is better than that of the second-order modulator with steeper noise shaping slope.

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Fully differential CMOS sigma-delta modulator for high performance analog-to-digital conversion with 5 V operating voltage

10.1109/iscas.1988.15409 ◽

2003 ◽

Cited By ~ 10

Author(s):

T. Ritoniemi ◽

T. Karema ◽

H. Tenhunen ◽

M. Lindell

Keyword(s):

High Performance ◽

Operating Voltage ◽

Digital Conversion ◽

Sigma Delta Modulator ◽

Sigma Delta ◽

Analog To Digital ◽

Fully Differential ◽

Analog To Digital Conversion

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Low Power, High Dynamic Range CMOS Image Sensor Employing Pixel-Level Oversampling $\Sigma\Delta$ Analog-to-Digital Conversion

IEEE Sensors Journal ◽

10.1109/jsen.2011.2158818 ◽

2012 ◽

Vol 12 (4) ◽

pp. 737-746 ◽

Cited By ~ 24

Author(s):

Zeljko Ignjatovic ◽

Danijel Maricic ◽

Mark F. Bocko

Keyword(s):

Low Power ◽

Dynamic Range ◽

High Dynamic Range ◽

Cmos Image Sensor ◽

Image Sensor ◽

Digital Conversion ◽

Sigma Delta ◽

Analog To Digital ◽

Analog To Digital Conversion ◽

High Dynamic

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A 8X Oversampling Ratio, 14bit, 5-MSamples/s Cascade 3-1 Sigma-delta Modulator

Advances in Radio Science ◽

10.5194/ars-3-277-2005 ◽

2005 ◽

Vol 3 ◽

pp. 277-280

Author(s):

Y. Yin ◽

H. Klar ◽

P. Wennekers

Keyword(s):

Noise Shaping ◽

Digital Conversion ◽

Sigma Delta Modulator ◽

Sigma Delta ◽

Analog To Digital ◽

High Frequencies ◽

Analog To Digital Conversion ◽

Sigma Delta Adc ◽

Oversampling Ratio ◽

Ic Technology

Abstract. A 14-b, 5-MHz output-rate cascaded 3-1 sigma-delta analog-to-digital converters (ADC) has been developed for broadband communication applications, and a novel 4th-order noise-shaping is obtained by using the proposed architecture. At a low oversampling ratio (OSR) of 8, the ADC achieves 91.5dB signal-to-quantization ratio (SQNR), in contrast to 71.8dB of traditional 2-1-1 cascaded sigma-delta ADC in 2.5-MHz bandwidth and over 80dB signal-to-noise and distortion (SINAD) even under assumptions of awful circuit non-idealities and opamp non-linearity. The proposed architecture can potentially operates at much more high frequencies with scaled IC technology, to expand the analog-to-digital conversion rate for high-resolution applications.

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