Wafer Level Integrated Antenna Front End Module For Low Cost Phased Array Implementation

Author(s):  
J. M. Yang ◽  
Y. Chung ◽  
M. Nishimoto ◽  
M. Battung ◽  
A. Long ◽  
...  
Author(s):  
Jong-Min Yook ◽  
Dongsu Kim ◽  
Bok-Ju Park ◽  
Sanghoon Sim ◽  
Yun-Seong Eo ◽  
...  

Author(s):  
Jyh-Rong Lin ◽  
Yeung Yeung ◽  
Ruonan Wang ◽  
Bin Xin ◽  
Lydia Leung ◽  
...  

Author(s):  
M. Tentzeris ◽  
J. Laskar

This paper presents the development of RF System-on-Package (SOP) architectures for compact and low cost wireless radio front-end systems. A novel 3D integration approach for SOP-based solutions for wireless communication applications is proposed and utilized for the implementation of a C band Wireless LAN (WLAN) RF front-end module by means of stacking LTCC substrates using μBGA technology. LTCC designs of high-performance multilayer embedded bandpass filters and novel stacked cavity-backed patch antennas are also reported. In addition, the fabrication of very high Q-factor inductors and embedded filter in organic substrates demonstrate the satisfactory performance of multilayer organic packages. The well known full-wave numerical techniques of FDTD and MRTD are used for the modeling of adjacent lines crosstalk, of the Q-factor of embedded passives and for the accurate simulation of MEMS structures.


Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1893
Author(s):  
Faxin Yu ◽  
Qi Zhou ◽  
Zhiyu Wang ◽  
Jiongjiong Mo ◽  
Hua Chen

In this paper, a three-dimensional heterogenous-integrated (3DHI) wafer-level packaging (WLP) process is proposed, and a radio frequency (RF) front-end module with two independent ultra-high frequency (UHF) receiving channels are designed and implemented, which covers 400 MHz–600 MHz and 2050 MHz–2200 MHz respectively for unmanned aerial vehicle (UAV) applications. The module is formed by wafer-to-wafer (W2W) bonding of two high-resistivity silicon (HR-Si) interposers with embedded bare dies and through silicon via (TSV) interconnections. Double-sided deep reactive ion etching (DRIE) and conformal electroplating process are introduced to realize the high-aspect-ratio TSV connection within 290 µm-thick cap interposer. Co-plane waveguide (CPW) transmission lines are fabricated as the process control monitor (PCM), the measured insertion loss of which is less than 0.18 dB/mm at 35 GHz. The designed RF front-end module is fabricated and measured. The measured return loss and gain of each RF channel is better than 13 dB and 21 dB, and the noise figure is less than 1.5 dB. In order to evaluate the capability of the 3DHI process for multi-layer interposers, the module is re-designed and fabricated with four stacked high-resistivity silicon interposers. After W2W bonding of two pairs of interposers and wafer slicing, chip-to chip (C2C) bonding is applied to form a four-layer module with operable temperature gradient.


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